clock tree synthesis questions

[ebuddy]

Hi

When synthesize clock tree in SOC encounter, one needs to specify the clock tree spec, like the one below:

MaxDelay 10ns
MinDelay 0ns
MaxSkew 200ps
SinkMaxTran 400ps
BufMaxTran 400ps

Question: what is the resonable number to specify for each of the field? Why people care about the MaxDelay and MinDelay? Is 200ps a good skew number to specify for MaxSkew? Thanks.

Ebuddy

 

[lostinxlation]

Why people care about the MaxDelay and MinDelay?

1. To meet power budget.
2. To avoid excessive effect from OCV.

 

[ebuddy]

Thanks for the answer.

So by specifying MaxDelay, you can control the number of stages in the clock tree, thus control number of buffers, which decides the CKT power consumption?

For MinDelay, by specifying min delay, the tool will insert some buffers, which increases the contributing elements to the insertion delay. Assuming random OCV, the variation will cancel each other and the CKT will give us better result?

Am I on the right track understanding your comments or I am totally off? Could you elaborate a little more? Thanks.

 

[lostinxlation]

By nature of OCV, the longer the clock insertion delay is, the greater the variation will be, which ends up with much greater clock skew than the tree with shorter clock insertion delay.

 

[ebuddy]

By nature of OCV, the longer the clock insertion delay is, the greater the variation will be, which ends up with much greater clock skew than the tree with shorter clock insertion delay.

Well, if that is the case, then I still don't understand why people want to specify MinDelay then. Under what situation when it makes sense for people to specify a min delay?

 

[lostinxlation]

Well, if that is the case, then I still don't understand why people want to specify MinDelay then. Under what situation when it makes sense for people to specify a min delay?

Too short clock insertion delay won't work. For exmaple, think of the setup analysis on the path going into clock gating cells.

---------- Post added at 06:32 ---------- Previous post was at 05:29 ----------

I'll take back what I said. In general, shorter insertion delay is always good.

 

[phoenixpavan]

Let me put it this way

Min insertion delay = Min no of buffers to be added = Increase in clock signal strength = Clock signal will be driven more effectively in the clock tree

Is the above analysis right?

 

[lostinxlation]

Let me put it this way

Min insertion delay = Min no of buffers to be added = Increase in clock signal strength = Clock signal will be driven more effectively in the clock tree

Is the above analysis right?

the strength of clock signal only depends on the drive strength and loads. Insertion delay is irrelevant.
But if you can make clock tree shorter, it is more effective in terms of area and power as well as timing closure.

I do agree with OP. From implementation point of view, there is no reason to require the min delay, but my guess is software somehow needs that information to make the algorithm work efficiently.

 

[owen_li]

Hi ebuddy.

I have implemented the min insertion delay in previous project.
It is useful when you conduct a hierarchical design.
If you want to balance clock trees across two or more blocks, you can set the min insertion delay for some blocks with short clock tree path.
Then it will ease you to insert padding to balance the clock trees across some blocks.

Thanks!

 

[phoenixpavan]

Thank you guys, it was helpful

 

[hari151087]

Thank you guys, it was helpful