Clock Tree Synthesis of a delay chain (tapped delay line)

[srieda]

In RTL, clock buffers and MUXes are used to create a delay chain/tapped delay line. These are preserved in synthesis and hence they appear in the netlist.
If this netlist is used, during Clock Tree Synthesis (CTS) stage, the tool (SoC Encounter) hangs and does not move forward saying that the clocks are already built and cannot be removed. If delete clock tree option is removed and CTS is run again, it comes out with a message that the clock has already been built and will not move forward.

Any idea as to how to proceed with CTS for this?

 

[Kuxx]

Hi.

1. You can delete your chain from RTL and use set_clock_latency constraint during synthesis to obtain correct SDF for simulation.
2. If it's important to preserve this chain during synthesis and in the layout stage you can declare your clock in SDC at the end pin of this chain, not at start pin/port.
3. If this chain is not needed after synthesis you can delete it from netlist before loading design into Encounter or to delete module with this gates using Encounter console.

Please provide more info what you want: just simulate clock delay after synthesis or to preserve this chain in layout design.

Hope it's helpful.

Best regards,
Kuxx.