Clock Tree Synthesis - CTS

[Ikon]

Hi ,

I have a question regarding Clock Tree Synthesis.

I have a design, and I need to run CTS on the design.

1. How do I decide on the number of levels of buffers required for the clock tree?
either it is 0 level or 1 level or 2 levels ?

thanx

 

[xysafety]

in my opinion,
Setting level of clock is not necessary. Just set the clock skew. max clock insertion delay is enough

 

[dreamscome]

Let Tools do that for you

 

[suituse]

Use the cts tools first, and do some manual modification if the skew and clock tran are not good enough for you.

 

[beckchm]

In general , you can set the max skew ,transition time and so on .

 

[zhanch]

The tools can automatically do this for you

 

[jcchan]

You must discuss with EDA some times the constraint you define can not to do.

 

[pratap_v]

First know the number of sink pins i mean register/Flops in the design. If they are 1000 for instance, and let say 20 is the fanout for a buffer. To drive 1000 flops you need atleast now 1000/20 (50) buffers, and you need 3 buffers to drive this 50 buffers.
So, you need 50 buffers at the 3rd level and buffers at 2nd level and 1 driving cell at 1st level.

 

[cihchenlin]

very good,

 

[srideepa]

Level will generally 3 for a design with more than 200 K gate count.We can calculate using the method described before but that should be used for number of flops clocked by the functional/main clock.

In general,it doenst matter how many levels we have as long as skew and insertion delay targets are met. We can have 3 BUFX16 or 5 BUFX4 . The size of the former will still be bigger when compared with latter. Deciding on the optimum buffers/inverters that are to be used( general idea is to remove smallest and largetst buffers) in CTS and realistic skew and network latency targets will help us to keep utilization & timing under control.

 

[nitin kala]

Hi All,
Please share any scripts for h-tree manual Clock tree synthesis technique.
Thanks,
Nitin