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[Clock Tree] Gated Clock

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ivlsi

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Hello All,

What're rules for the Clock Tree/Domain definitions?

Will insertion a Gated Clock Cell introduce a new Clock Domain?

Thank you!
 

Inserting a clock gating cell will not create NEW CLOCK DOMAIN
 
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    ivlsi

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Does a generated clock (output from a flop) create a new Clock Domain?
What criteria/cause/reason for creation a new clock domain (generated clock, etc)?
Thank you!
 

Does a generated clock (output from a flop) create a new Clock Domain?
What criteria/cause/reason for creation a new clock domain (generated clock, etc)?
Thank you!



Hi ,
From my knowledge generated clock wont be consider as new clock domain.Reason behind is each clock source will have its own exception in terms of gitter,latence etc and these will be present in SDC. So generated clock will not consider as new clock domain so what ever exception for actual source the same exception will be foreword to generated clock. Again no need of mention in SDC.

If wrong please correct me
 

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