Clock too slow to detect rising/falling edge?

[crz]

I'm trying to sending a serial data out from a fpga to microprocessor.
uP sends a 8.4MHz bit clock to FPGA, and FPGA needs to send the data on the rising edge of the bit clock because uP samples the data on the falling edge of the bitclock.

bitclock is not synchronized to FPGA's internal 50MHz clock.

Is FPGA's internal 50MHz clock too slow to detect the rising edge of the bitclock?

Since bitclock is not synchronized to 50MHz, I am using double flip flops to detect the rising edge of bitclock.

under my process(ck_50mhz) I have:
...
bitclock_d <= bitclock;
bitclock_d2 <= bitclock_d;

if(ck_50mhz'event and ck_50mhz='1') then
if (bitclock_d = '1' and bitclock_d2 = '0') then
serial_data <= sh_reg;
...
end if;
end if;


My concern is:
worst case, serial_data will appear 60ns (20ns for 1st flop + 20ns for 2nd flop + 20ns later data will appear outside the fpga) after rising edge of bitclock, which is too late for the uP to latch the data since uP latches the data on the falling edge.

Is that true?

What can I do to resolve this? Updating clock's and the bitclock's frequencies is not an option.

Previously I tried using bitclock for my process, instead of using 50MHz internal clock, but that complicated the whole design and I got so much timing violations.

Thanks.

 

[FvM]

From a certain clock speed, the SPI slave SR must be clocked by the SPI clock directly. Of course the clock domain crossing must be realized properly, then it won't cause timing violations.

As another option, you can reduce the synchronous edge detection latency by using both edges of the 50 MHz system clock.