sample clock fpga clock
From your description, it sounds like the FPGA clock is leading the SDRAM clock by some amount. Since you receive a constant logic "1", it sounds like you are not close to a clock edge. Therefore, it seems that all you require is to take the SDRAM input and double buffer it with two flops in the FPGA clock domain. This is usually the preferred method. You really cannot sync two clocks that are at an arbitrary phase relationship unless you use a PLL or DLL.
However, in cases like yours where the frequencies are the same, you do not need to sync. All you need to do is to insure that you can pass data between the two clock domains. We have done numerous FPGAs over the years that require 5-10 different clocks at different phase relationships to a master clock. In order to pass the data, we use a meta circuit. The meta circuit either passes the data using the rising edge of the sample clock or the falling edge of the sample clock. We use which ever one gives that best timing margins for that particular clock. Often either clock edge works just fine. However, when we are very clock to a clock transition, switching to the other clock edge always clears up the issues. Within the meta circuit, we set our timing fairly tight so that we can make timing from the negative edge of the sample flop to the rising edge of the next flop. That insures that all downstream logic can use the rising edge of the clock and we do not have to switch over entire sections of the FPGA.