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Clock Stretching in I2C

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Jun 11, 2007
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i2c clock stretching

Can you tell me how to implement clock stretching in I2C

clock stretching in i2c

You might have counter to generate the clock. If you don't receive the ack then you need to implement the clock streching. If you want to strech the clock to enable the couneter for counting. In that wat you will be able to strech it. If you are generating clock with other method pls let me know so that I can suggest according idea.

clock stretching, i2c

you can wait for consecutive 3 or more (i restarted transmission with START if i didn't receive for 3 scl clocks) clock cycles if you don't get ACk on sda.
but if the device with which you are communicating with i2c protocl is fully supprorting it then it;'ll definitely generate ACk at nineth clock cycle.
hope it helps.

clock stretching of i2c

My reply is quite different from the above two..
Clock stretchin is employd when the slave has read or writtn the data to the master but has to wait to finish the task like for e.g. an ADC converter, it wil employ clock stretching and after it has finishd its task, it will release the SCL and process to send/receive ACK signal.

clock streching is always done after getting ack signal only. If slave has to make wait master then it will pull down the SCL
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clock streching is always done after getting ack signal only. If slave has to make wait master then it will pull down the SCL

u got mistake "clock streching is always done before getting ack signal only" right?

From NXP i2c specs

3.1.9 Clock stretching
Clock stretching pauses a transaction by holding the SCL line LOW. The transaction
cannot continue until the line is released HIGH again. Clock stretching is optional and in
fact, most slave devices do not include an SCL driver so they are unable to stretch the
On the byte level, a device may be able to receive bytes of data at a fast rate, but needs
more time to store a received byte or prepare another byte to be transmitted. Slaves can
then hold the SCL line LOW after reception and acknowledgment of a byte to force the
master into a wait state until the slave is ready for the next byte transfer in a type of
handshake procedure (see Figure 7).
On the bit level, a device such as a microcontroller with or without limited hardware for the
I2C-bus, can slow down the bus clock by extending each clock LOW period. The speed of
any master is adapted to the internal operating rate of this device.
In Hs-mode, this handshake feature can only be used on byte level (see Section 5.3.2).

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