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Clock skew > data delay in Altera Stratix

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jarodz

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clock skew > data delay

I have a design that using two memory bank to change the order of sequence.
When a memory bank is be writen, the other is be read.
Since the clock rate of read/write clock is different, I must use mux to select
read/write clock to clock pin of ram(One port, seperate data in/data out).
The problem I meet is, the mux clock is almost 7ns that is large the data delay about 2~3 ns.
Could anyone give some suggestion?
Any constrain can be used to fix this problem?

How to set clock timing to internal mux clock(combination net) before synthesis?
When I re-syn, the internal node is changed?
I must be re-select the node everytime.

I claim that I must use single-port to design the project because of the area concern. The FPGA is just a prototype to verify Function. Finally, it will be a ASIC.

I use Quatus-II to synthesis/placement route.
 

clock skew data delay

I find the method to solve my problem.
My design is synthesised by synpilfy with synpilfy synthesis attribute as below.
/* synthesis syn_keep */ to keep the net name after synthesis.
At the APR stage in Quatus, define the mux clock as new clock(set clock constrain),
then use multi-cycle hold/setup constrain between pre-mux clock and post-mux clock to fix this problem.

My question is the clock constrain seems that it can be cross clock mux, but why it don't fix the clock skew?


Regards,
Jarod
 

stratix clock mux

perhaps you can change your design into a dualport ram,

thus that will be less problem.

best regards





jarodz said:
I have a design that using two memory bank to change the order of sequence.
When a memory bank is be writen, the other is be read.
Since the clock rate of read/write clock is different, I must use mux to select
read/write clock to clock pin of ram(One port, seperate data in/data out).
The problem I meet is, the mux clock is almost 7ns that is large the data delay about 2~3 ns.
Could anyone give some suggestion?
Any constrain can be used to fix this problem?

How to set clock timing to internal mux clock(combination net) before synthesis?
When I re-syn, the internal node is changed?
I must be re-select the node everytime.

I claim that I must use single-port to design the project because of the area concern. The FPGA is just a prototype to verify Function. Finally, it will be a ASIC.

I use Quatus-II to synthesis/placement route.
 

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