jarodz
Full Member level 1
clock skew > data delay
I have a design that using two memory bank to change the order of sequence.
When a memory bank is be writen, the other is be read.
Since the clock rate of read/write clock is different, I must use mux to select
read/write clock to clock pin of ram(One port, seperate data in/data out).
The problem I meet is, the mux clock is almost 7ns that is large the data delay about 2~3 ns.
Could anyone give some suggestion?
Any constrain can be used to fix this problem?
How to set clock timing to internal mux clock(combination net) before synthesis?
When I re-syn, the internal node is changed?
I must be re-select the node everytime.
I claim that I must use single-port to design the project because of the area concern. The FPGA is just a prototype to verify Function. Finally, it will be a ASIC.
I use Quatus-II to synthesis/placement route.
I have a design that using two memory bank to change the order of sequence.
When a memory bank is be writen, the other is be read.
Since the clock rate of read/write clock is different, I must use mux to select
read/write clock to clock pin of ram(One port, seperate data in/data out).
The problem I meet is, the mux clock is almost 7ns that is large the data delay about 2~3 ns.
Could anyone give some suggestion?
Any constrain can be used to fix this problem?
How to set clock timing to internal mux clock(combination net) before synthesis?
When I re-syn, the internal node is changed?
I must be re-select the node everytime.
I claim that I must use single-port to design the project because of the area concern. The FPGA is just a prototype to verify Function. Finally, it will be a ASIC.
I use Quatus-II to synthesis/placement route.