Hi Viju,
my 2 cents viju
Scenario from a Timing analysis Tool
Startpoint: flop1
(rising edge-triggered flip-flop clocked by clk1)
Endpoint: flop2
(rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: min
Point Incr Path
-------------------------------------------------------------------------
clock clk1 (rise edge) 0.000 0.000
clock network delay (propagated) 1.500 1.500
flop 1/CP (library flop1 cell name)
0.000 1.500 r
flop 1/Q (library flop1 cell name)
0.220 & 1.720 r
flop 2/D (library flop2 cell name)
0.000 & 1.720 r
data arrival time 1.720
clock clk1 (rise edge) 0.000 0.000
clock network delay (propagated) 1.720 1.720
[Clock tree + ck-q]
flop 2/CP (library flop2 cell name)
1.720 r
library hold time 0.040 1.760
data required time 1.760
--------------------------------------------------------------------------
data required time 1.760
data arrival time -1.720
--------------------------------------------------------------------------
slack (VIOLATED) -0.040
One very important point to be remembered during Timing Analysis
For setup check
"data required time - data arrival time"
For hold check
"data arrival time - data required time"
hope i made it clear and not confused.
For better understanding the concepts of static timing analysis
https://www.vlsichipdesign.com/static_timing_analysis.html
Always Praise the Lord
best regards,
vlsichipdesigner
https://www.vlsichipdesign.com
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