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Clock oscillator at sleep mode

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shaiko

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I'm using an FPGA in 2 clock domains.
The first clock is a very slow 32KHz - active all the time
The second clock 100MHz is inactive when the circuit is in sleep mode - This is done by disabling the "output enable" pin of the clock oscillator.

The problem is that when the output of the 100MHz clock is disabled it's high 'Z'.
I'm a little reluctant to keep this clock pin floating - Any suggestions ?
Is it a good idea to use an external weak pull-up ?
 

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