Apologies my description is vague, still extremely new to this. I mean a physical chip that is actually generating a clock. I understand how to manipulate the signal once it reaches the CPLD.Hi,
I don't understand.
To generate a PWM you first need to consider:
* expected PWM frequency (range)
* resolution (steps)
PWM module basically is just a (binary) counter and a (binary) comparator.
..maybe a flipflop for the output
Multiply PWM_frequency with resolution to get counter_clock_frequency
Example: PWM_frequency = 1 kHz, resolution = 256 steps
--> Counter_clock_frequency = 256 kHz
To generate the Counter_clock_frequency:
don't use clock dividers to generate a new_clock,
but use dividers to generate a count_enable_signal
Ok perfect, thank you. I was searching clock modules (coming from arduino) but the refined search of clock_oscillator pinpoints exactly what I have been trying to search for.Hi,
Yes, the CPLD needs a clock.
The requirements according frequency range, and voltage levels are given in the CPLD datasheet.
There are many clock_oscillator manufacturers and even more clock_oscillator types.
Many are suitable.
The first thing you need to do:
Decide your requirements. The voltage levels are given. So basically you need to decide the frequency.
* If possible use only one clock source for CPLD internal logic
* focus on those parts (frequencies) that need a very fixed clock (no "range". Like UART, USB...).
* A higher frequency clock gives more flexibility (as you can simply divide it down)