Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Clock module recommendations

Status
Not open for further replies.
Joined
Jul 22, 2021
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
22
Hi, I'm trying to create a PWM to control a servo motor, and was wondering what a good clock module to use would be.
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
19,944
Helped
4,370
Reputation
8,749
Reaction score
4,352
Trophy points
1,393
Activity points
132,017
Hi,

I don't understand.

To generate a PWM you first need to consider:
* expected PWM frequency (range)
* resolution (steps)

The
PWM module basically is just a (binary) counter and a (binary) comparator.
..maybe a flipflop for the output

With
Multiply PWM_frequency with resolution to get counter_clock_frequency
Example: PWM_frequency = 1 kHz, resolution = 256 steps
--> Counter_clock_frequency = 256 kHz

As always:
To generate the Counter_clock_frequency:
don't use clock dividers to generate a new_clock,
but use dividers to generate a count_enable_signal

Klaus
 

dpaul

Advanced Member level 4
Joined
Jan 16, 2008
Messages
1,489
Helped
307
Reputation
614
Reaction score
304
Trophy points
1,373
Location
Germany
Activity points
11,159
and was wondering what a good clock module to use would be
Assuming you want to make an FPGA based design, it depends on which FPGA you are using. Unfortunately you have not explained anything in details.
 

Joined
Jul 22, 2021
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
22
Hi,

I don't understand.

To generate a PWM you first need to consider:
* expected PWM frequency (range)
* resolution (steps)

The
PWM module basically is just a (binary) counter and a (binary) comparator.
..maybe a flipflop for the output

With
Multiply PWM_frequency with resolution to get counter_clock_frequency
Example: PWM_frequency = 1 kHz, resolution = 256 steps
--> Counter_clock_frequency = 256 kHz

As always:
To generate the Counter_clock_frequency:
don't use clock dividers to generate a new_clock,
but use dividers to generate a count_enable_signal

Klaus
Apologies my description is vague, still extremely new to this. I mean a physical chip that is actually generating a clock. I understand how to manipulate the signal once it reaches the CPLD.

The hardware im using is the Xilinx CoolRunner-II CPLD Processor, C-Mod Board. From my understanding the chip does not have an inbuilt clock and requires an external one to be connected.

If you need further information I will clarify.

Thanks for your patience!
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
19,944
Helped
4,370
Reputation
8,749
Reaction score
4,352
Trophy points
1,393
Activity points
132,017
Hi,

Yes, the CPLD needs a clock.

The requirements according frequency range, and voltage levels are given in the CPLD datasheet.

There are many clock_oscillator manufacturers and even more clock_oscillator types.
Many are suitable.

The first thing you need to do:
Decide your requirements. The voltage levels are given. So basically you need to decide the frequency.

My recommendations:
* If possible use only one clock source for CPLD internal logic
* focus on those parts (frequencies) that need a very fixed clock (no "range". Like UART, USB...).
* A higher frequency clock gives more flexibility (as you can simply divide it down)

Klaus
 
Last edited:
Joined
Jul 22, 2021
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
22
Hi,

Yes, the CPLD needs a clock.

The requirements according frequency range, and voltage levels are given in the CPLD datasheet.

There are many clock_oscillator manufacturers and even more clock_oscillator types.
Many are suitable.

The first thing you need to do:
Decide your requirements. The voltage levels are given. So basically you need to decide the frequency.

My recommendations:
* If possible use only one clock source for CPLD internal logic
* focus on those parts (frequencies) that need a very fixed clock (no "range". Like UART, USB...).
* A higher frequency clock gives more flexibility (as you can simply divide it down)

Klaus
Ok perfect, thank you. I was searching clock modules (coming from arduino) but the refined search of clock_oscillator pinpoints exactly what I have been trying to search for.

The other tips are much appreciated :D
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
19,944
Helped
4,370
Reputation
8,749
Reaction score
4,352
Trophy points
1,393
Activity points
132,017
Hi,

when I read "Arduinio" I think of the many users here to run such designs on a breadboard.
--> Please don´t waste your time with a breadboard. It is not suitable for high frequency signals.

****
Frequency selection:
Let´s imagine you need
* a PWM frequency range of 1000Hz to 2000Hz with 256 steps resolution.
* a UART with baud rate of 38400 and 8 times oversampling
* A microcontroller that needs 8 MHz

Maybe the microcontroller has a built in software RTC, then it needs a very accurate clock. no additional error.
The UART will work with a clock frequency error of +/-2%
The PWM frequency is uncritical at all.

so you need to look for a clock (uC) that has multiple integer of 8MHz --> 8, 16, 24, 32, 40, 48...MHz
Now you have to check UART frequency. 38400Hz x 8 = 307.8 kHz
8M / 307.8k = 26.04167 --> the next best integer is 26
now calaculate frequency error: (26 - 26.04167)/ 26.04167 = 0.0016 = 0.16% --> within +/-2%, so it´s O.K.

Although this says you may use a 8MHz oscillator, I´d recommend a 48MHz one for more flexibility.
(please do error calculations before buying)

Klaus
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top