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clock jitter effect on ADC outputs

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s55

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I have some questions about an ADC performance using jittery clock.

Here are some questions to be used in my questions.
Let's ignore other noise sources except the quantization and the clock jitter for simple discussion.

SNR_j = -20 log(tj * 2*pi * fo) --- (eq.1)
= 10 log (P_sig / P_j) --- (eq.2)

where SNR_j: SNR between the signal power and the jitter induced noise power
tj: rms clock jitter and fo: ADC input signal frequency.
fo: ADC output signal frequency
P_sig: signal power in watt
P_j: jitter induced noise power in watt

Here are my questions:

1. Theoretically, the sum of the signal power and the harmonics' power at the ADC output is supposed to be reduced by the amount of the total phase noise power caused by the clock jitter. Then, I calculated that total reduced power, ignoring the harmonics' power portions for simple discussion, as

For example, assuming tj = 20 ps_rms, fo = 10 MHz, and the signal power is 10mW or 10dBm (ie. swing signal from +1v to -1v) then
(using (eq.1))
SNR_j = -20 log(tj * 2*pi * fo) = 58dB

(using (eq.2))
SNR_j = 10 log (P_sig / P_j)
P_j = P_sig / (10^(SNR_j / 10)) = 15.8nW

The reduced signal power is then: P_sig - P_j = 10mW - 15.8nW = 0.0099999842 W
or 10 log (0.0099999842W / 1mW) = 9.9999931 dBm (it's still almost 10dBm)

Personally, 20ps of the clock jitter is too high for an ADC operation, and so I expected the fundamental signal power would be significantly reduced, but it is not reduced at all, as seen in my calculation. Please correct my derivation, if any.


2. It is known that the clock jitter causes 2 types of the phase noises: the close-in phase noise and the broadband phase noise.
If we know the clock-jitter induced noise, 15.8nW, then can we split it to the close-in phase noise power and the broadband phase noise? If yes, then how can we calculate it?
 

KlausST

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Hi,

Edit: the following statement is wrong (grey) .
don´t add or subtract power in a usual way: like Ptot = P1 + P2 + P3...

add them this way: Ptot = sqrt( P1^2 + P2^2 + P3^2 ...)


Then the reduced power is even less.

But does phase jitter really reduce the fundamental? I rather think it adds new frequency components and the total power increases. But I´m not sure with this.
Anyway it has very low influence on total or fundamental power. Often negligible.

Klaus
 
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s55

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Thanks for the quick help, KlausST.

> add them this way: Ptot = sqrt( P1^2 + P2^2 + P3^2 ...)
I actually thought,
Vtot_rms^2 = V1_rms^2 + V2_rms^2 + V3_rms^2 + ...
Vtot_rms^2 / R = V1_rms^2 / R + V2_rms^2 / R + V3_rms^2 / R + ...
Ptot = P1 + P2 + P3 + ...
where R means the ADC circuitry shared with noises and signals.
Please correct me, if i'm still wrong...
 

KlausST

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Hi,

Sorry, my mistake. You are right.
Add power as usual and voltage with square and sqrt.

Klaus
 

s55

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I'm the person who posted the original questions above.
I'm still waiting for the answers of every single question now...

Here are the key point I'm focusing on for each original question:
Question 1: confirm the whole procedure in my derivation. (actually, I have experimentally measured the reduced power of the fundamental signal, and it was not such low, unlike my derivation.)
Question 2: I'm really looking for the way to split to the close-in phase noise and the broadband phase noise, due to some reason.

Any body who can help on this?
 

FvM

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It is known that the clock jitter causes 2 types of the phase noises: the close-in phase noise and the broadband phase noise.
Can you give a short hint or a link how broadband noise is generated by mixing a signal with a noisy clock signal which has essentially very small (e.g. kHz) bandwidth?

Reduction of the signal power by noise power sounds plausible, depending on jitter amount, measurement accuracy and resolution bandwidth, the reduction may be beyond measurability. I don't think that it's usually of much interest.
 

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