clock issues for deep subicron

[gokulka]

Please smeone give detais about clock issues for deep sub micron technology.

thanks:

 

[phoenixpavan]

The issues(skew/latency/SI) are still the same i guess, only the contribution of factors(process variation etc) effecting these will vary

 

[GI]

Hi gokulka,

Firstly, clock skew and clock latency (related to clock tree depth) are the most important problems to solve in clock tree synthesis.

Secondly, design rule violations such as maximum transition on clock pins, maximum capacitance, maximum fanout, and clock bumps (signal integrity issues) are important factors.

For a typical design, one wants a design having the smallest skew (assuming no useful skew is used), with the smallest insertion delay without any design rule violations and bumps originating from aggressor nets.

There are known solutions for most of these problems, and there are Clock Tree Synthesis engines from EDA vendors targeting to solve these issues.

BR,
Gokhan
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[kumar_eee]

In deep sub-micron technologies, The following points play an important role.

1.Clock skew
2.Clock transition
3.Clock routing ( Non-Default Rules ) & Shielding
4.Clock Insertion delay ( due to the increase in gate-count ).
5.SI related parameters.

Keeping all the parameters under control is really a challenging task.

Others can add their points.

Rgds,
Kumar