Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

clock generator circuit (÷2 and ÷3)

Status
Not open for further replies.

casanova105

Newbie level 3
Joined
Feb 11, 2006
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,306
can anyone help desinging clock generator ÷2 and ÷3 with 50 % duty cycle, (using logic gates and flip flops) please
 

ceaser

Advanced Member level 4
Joined
Dec 26, 2005
Messages
112
Helped
13
Reputation
26
Reaction score
5
Trophy points
1,298
Location
Egypt
Activity points
2,681
i think you should write a VHDL code on FPGA with modelsim using library "arith"
then you can see the corresponding logic gates
any way to have clk freq half the original one you can pass this clk into T-ff positive edge

Regards
 

m_kartik

Newbie level 6
Joined
Feb 7, 2006
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,358
For divide by 2, you can simply pass the clock signal through a FF...
and i don't think it is possible to get divide by 3, with 50% duty cycle.
 

jetset

Full Member level 3
Joined
Jun 17, 2004
Messages
153
Helped
14
Reputation
28
Reaction score
3
Trophy points
1,298
Location
Panama
Activity points
1,256
To divide by 2 is simple just use a T-ff, or equivalent.

To divide by 3, you should use a state machine like the one described in this table:


Current state Next state Output(divided by 3)
--------------- ------------ ------------------------
S0 -------------------->S1--------------------->1
S1 -------------------->S2 -------------------->1
S2 -------------------->S3 -------------------->1
S3 -------------------->S4 -------------------->0
S4 -------------------->S5 -------------------->0
S5 -------------------->S0 -------------------->0


So, now that you have the transition table, you can easily create the circuit, or write the HDL code.
 

vsgiri

Member level 5
Joined
Feb 24, 2006
Messages
86
Helped
10
Reputation
20
Reaction score
3
Trophy points
1,288
Activity points
2,140
I'm sorry I have to disagree with jetset with the state transition table.
According to that, we have in one period of the o/p, 6 clk cycles of the i/p. So it's in fact a divide by 6 counter with 50% duty cycle.

To have a divide by 3, 50% duty cycle,here's a method.
Make a divide-by-3 counter that works on positive edge and negative edge that does not have 50% duty cycle.
State mapping
S0->S1->0
S1->S2->0
S2->S0->1

Now just or the two outputs - you have divide-by-3 50% duty cycle!
Welcome comments.

Giri
 

jetset

Full Member level 3
Joined
Jun 17, 2004
Messages
153
Helped
14
Reputation
28
Reaction score
3
Trophy points
1,298
Location
Panama
Activity points
1,256
vsgiri said:
I'm sorry I have to disagree with jetset with the state transition table.
According to that, we have in one period of the o/p, 6 clk cycles of the i/p. So it's in fact a divide by 6 counter with 50% duty cycle.

To have a divide by 3, 50% duty cycle,here's a method.
Make a divide-by-3 counter that works on positive edge and negative edge that does not have 50% duty cycle.
State mapping
S0->S1->0
S1->S2->0
S2->S0->1

Now just or the two outputs - you have divide-by-3 50% duty cycle!
Welcome comments.

Giri


Oh, sorry you're right, maybe for a "either edge machine" my table would work.

Anyway, another solution would be to use two state machines with this state transition:

cs ns out
--- --- ---
S0-->S1--->1
S1-->S2--->1
S2-->S0--->0

One fed by a CLK signal, and the other fed by the negative of that CLK signal.

Then AND the outputs of both machines, and there's your divide by 3.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top