casanova105
Newbie level 3
can anyone help desinging clock generator ÷2 and ÷3 with 50 % duty cycle, (using logic gates and flip flops) please
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vsgiri said:I'm sorry I have to disagree with jetset with the state transition table.
According to that, we have in one period of the o/p, 6 clk cycles of the i/p. So it's in fact a divide by 6 counter with 50% duty cycle.
To have a divide by 3, 50% duty cycle,here's a method.
Make a divide-by-3 counter that works on positive edge and negative edge that does not have 50% duty cycle.
State mapping
S0->S1->0
S1->S2->0
S2->S0->1
Now just or the two outputs - you have divide-by-3 50% duty cycle!
Welcome comments.
Giri