# clock generator circuit (÷2 and ÷3)

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#### casanova105

##### Newbie level 3
can anyone help desinging clock generator ÷2 and ÷3 with 50 % duty cycle, (using logic gates and flip flops) please

#### ceaser

##### Advanced Member level 4
i think you should write a VHDL code on FPGA with modelsim using library "arith"
then you can see the corresponding logic gates
any way to have clk freq half the original one you can pass this clk into T-ff positive edge

Regards

#### m_kartik

##### Newbie level 6
For divide by 2, you can simply pass the clock signal through a FF...
and i don't think it is possible to get divide by 3, with 50% duty cycle.

#### jetset

##### Full Member level 3
To divide by 2 is simple just use a T-ff, or equivalent.

To divide by 3, you should use a state machine like the one described in this table:

Current state Next state Output(divided by 3)
--------------- ------------ ------------------------
S0 -------------------->S1--------------------->1
S1 -------------------->S2 -------------------->1
S2 -------------------->S3 -------------------->1
S3 -------------------->S4 -------------------->0
S4 -------------------->S5 -------------------->0
S5 -------------------->S0 -------------------->0

So, now that you have the transition table, you can easily create the circuit, or write the HDL code.

#### vsgiri

##### Member level 5
I'm sorry I have to disagree with jetset with the state transition table.
According to that, we have in one period of the o/p, 6 clk cycles of the i/p. So it's in fact a divide by 6 counter with 50% duty cycle.

To have a divide by 3, 50% duty cycle,here's a method.
Make a divide-by-3 counter that works on positive edge and negative edge that does not have 50% duty cycle.
State mapping
S0->S1->0
S1->S2->0
S2->S0->1

Now just or the two outputs - you have divide-by-3 50% duty cycle!

Giri

#### jetset

##### Full Member level 3
vsgiri said:
I'm sorry I have to disagree with jetset with the state transition table.
According to that, we have in one period of the o/p, 6 clk cycles of the i/p. So it's in fact a divide by 6 counter with 50% duty cycle.

To have a divide by 3, 50% duty cycle,here's a method.
Make a divide-by-3 counter that works on positive edge and negative edge that does not have 50% duty cycle.
State mapping
S0->S1->0
S1->S2->0
S2->S0->1

Now just or the two outputs - you have divide-by-3 50% duty cycle!

Giri

Oh, sorry you're right, maybe for a "either edge machine" my table would work.

Anyway, another solution would be to use two state machines with this state transition:

cs ns out
--- --- ---
S0-->S1--->1
S1-->S2--->1
S2-->S0--->0

One fed by a CLK signal, and the other fed by the negative of that CLK signal.

Then AND the outputs of both machines, and there's your divide by 3.

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