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Clock Generation Verilog/VLSI

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Dino1400

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Assume we have an external clock, how I generate pulses that may have a 60 sec period and very small pulse width say 1sec, using a Verilog coding (not necessary 1/60 but could be any long period of seconds and a short pulse with)
Thank you all
 

Hi
I didn't understand your question correctly...
but I have to say that , "time" is not defined in HDL simulators like : Modelsim,ActiveHDL,Xilinx,...
I mean if you have a very short pulse width and your code is very long , then the simulator will simulate it correctly...
 

Let me tell you the whole story: Temperature Controller of a Water Tank
Verilog and VLSI design: I’m design a Temperature Controller of a Water Tank, I don’t have any idea in how to get the temperature from the water every probably 10min to compare with reference temperature (some 70 degrees) assume we know the clock frequency (some 10 KHz, T=100 us), the idea is to have two sensors getting samples every 10 min, take the average and turn ON the controller for period of time according to the deference. Example if the average is 55 degrees will turn the controller for 20min. just something like that.
THANK YOU ALL
 

well...
So what is the relationship between this project and Verilog?!!
why you don't use Microcontrollers?
 

Assume we have an external clock, how I generate pulses that may have a 60 sec period and very small pulse width say 1sec, using a Verilog coding (not necessary 1/60 but could be any long period of seconds and a short pulse with)

So your frequency is 0.0167 Hz and your "very small pulse width" is a humongous 1,000,000,000 ns. Why not just use an 8-bit microcontroller from the previous millenium? That will do the task just fine. No need do add the extra complexity of working with fpga's.

Same answer for the 10 kHz version. ;)
 
Hi,

Firstly considering your using a FPGA is rather an overkill you could use a simple 8051 microcontroller to do the job.
Nevertheless, you have a 10KHz clock and get a sample every 10 mins => generate a derived clock e.g. in verilog design a simple 16 bit counter and use the MSB transition as a clock for sampling your sensor inputs
The average of say input1, input2 ( your two sensor) e.g. average<=input1+input2; average_out<=average(8:2); essentially you right shift by 1 bit after the add.
The temperature controller pulse width i.e. the duty cycle you want the pulse for, you need to create a state machine style i.e. you have to decide at what temperature you want to have a certain pulse width.
Then quite simple create a FSM and plug the temp_controller variable there to get the corresponding output.

Have fun!
 

Your idea sounds good, couple questions here and there, do we take a sample every cycle of the counter say, when it arrive at 11111111111111111, sensor_1, and sensor_2, will check the temperature, the controller has a task that does the average and turn ON/OFF the warmer.
For a period of time that need to be calculated as will.
ALSO im not sure about the FSM usage with pulses.
If you can help me with more details I will appreciate that
 

do we take a sample every cycle of the counter say, when it arrive at 11111111111111111,
Conceptually Yes, but create an extra MSB bit so that your using only 1 bit combinational logic. Time wise I suggest you compute the number of bits according to your requirement.

im not sure about the FSM usage with pulses
Finite State Machine, is a simple concept which is used to abstract the application into a digital process. Few good books are i) Digital Design by Wakerly ii) Digital Design..Morris Mano
Besides Wiki!

Depending on how your temperature control to react you can design the FSM and the pulse width.

Good luck
 

Conceptually Yes, but create an extra MSB bit so that your using only 1 bit combinational logic. Time wise I suggest you compute the number of bits according to your requirement.

Finite State Machine, is a simple concept which is used to abstract the application into a digital process. Few good books are i) Digital Design by Wakerly ii) Digital Design..Morris Mano
Besides Wiki!

Depending on how your temperature control to react you can design the FSM and the pulse width.

Good luck

thanks you I appreciate your Ideas,
 

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