Clock Generation Block

[omara007]

Hi folks

If I'm isolating all generated clocks in one module .. with the source highest speed clock as an input .. and the all the required generated clocks are outputs .. should I use any reset or enable signals in this block ? ..
Simply, the block will contain a counter and each generated slower clock will be toggling with some counts of this counter .. but should this counter have a reset ? .. and enable ?

 

[koppolu1981]

Hi omara,
You need to have a reset in ur case also.
What will be the initial output of the counter if you do not assert reset...

Regards,
RamaMohan Rao K

 

[omara007]

Hi omara,
You need to have a reset in ur case also.
What will be the initial output of the counter if you do not assert reset...

Regards,
RamaMohan Rao K

You are correct .. and even each generated clock should have a reset value .. but what about the enable ? .. would that be equivalent to clock gating for them ? ..

 

[koppolu1981]

I think you should be using enable signal if your design needs it. The enable must be a functional signal. You must give enable as an input signal to the clock generation block if you are required to gate the clock in your design/ if you are clamping the clock.

- RamaMohan Rao K