clock gating while writing rtl

[sun_ray]

How do we write an rtl such that it includes necessary clock gating?

 

[slsindorf]

Present synthesis tools are able to recognize clock gate opportunities in RTL, and insert those clock gates.
There is no need to do anything in RTL, for example change something in the clock path.

You can still manually place clock gates in your RTL if you want too.

 

[tariq786]

Present synthesis tools are able to recognize clock gate opportunities in RTL, and insert those clock gates.
There is no need to do anything in RTL, for example change something in the clock path.

You can still manually place clock gates in your RTL if you want too.

Can you give examples of RTL code with clock gates manually inserted. This is to educate me and others.

Thanks

 

[sun_ray]

Present synthesis tools are able to recognize clock gate opportunities in RTL, and insert those clock gates.
There is no need to do anything in RTL, for example change something in the clock path.

Can you please let us know what command you will use of the synthesis tool so that tool itself will look in the portion of the rtls where clock gating is necessary and insert clock gating?

You can still manually place clock gates in your RTL if you want too.

What do you want to mean by this above statement? Is it that you are trying to say that we can even place clock gating cells in the rtls manually without using the feature of the tool for inserting clock gating cells whenver clock gating cells are required?

 

[slsindorf]

The following 2 approaches can be used independently:

a) Manual clockgate insertion
If you want to insert a clockgate in RTL, it looks like this:

cg_libcell u_cg0(
.enable (enable),
.clk_i (clk),
.clk_o (clk_gated)
);

Nothing special, just like any other instantiation.
Keep in mind that at synthesis you use a standard cell library that contains this cell 'cg_libcell'.
For simulation you need to compile a behavioral for this cell.

b) Synthesizer clock gate insertion (fine-grain insertion)
For options in your synthesis script it is better to start from a template script generated by RTL Compiler itself.
I believe "write_template" can do the trick.
It offers many options, I am sure at least one of them generates a script for clockgate insertion.

In this script you will find the enabling of clockgating, the choice for which cell to use, and the minimal amount of
registers the clockgate has to control.

Make sure that your RTL does have constructs that can actually be controlled by a clockgate:
- change or keep the register value
In RTL you see nothing in the clockpath itself.

Usually the synthesizer finds more clockgate possibilities than expected.