Clock Gating -> when it's worth to insert it manually?

[ivlsi]

Hi All,

When it's worth to insert Gated Clock manually in the Code or during BackEnd?

What cases are not covered by the Automatic Clock Insertion?

Thank you!

 

[ThisIsNotSam]

in my experience, writing code for clock gating is tremendously dumb. it kills ICs instead of saving power. let the tools handle it automatically.

 

[harpv]

It is beneficial to code clock gates into designs with a lot of clock branches. If majority of the clock tree for the branch gets built beyond such gate it'll save power when the clock is gated.

 

[ThisIsNotSam]

It is beneficial to code clock gates into designs with a lot of clock branches. If majority of the clock tree for the branch gets built beyond such gate it'll save power when the clock is gated.

not sure I follow. modern CTS tools can pick up common enables and propagate them up in the tree with ICG cells.

 

[George_P]

It is true that if you provide the enable to clocked processes the tools can take care of the clk gating.

However, if you have a block (e.g. an interface, SPI) that has an enable, then different processes inside this block will have additional enable/qualifiers to the main enable of the block. So the synthesis tool will build different gaters, for each enable.
This in not necessarily bad, but in some cases it may be beneficial (for power) to cut-off a block's clock centrally, so that it does not propagated to all these other gaters inside the block. So practically introduce manually, multi-stage clk gating.

Hope it helps
BR

Hi All,

When it's worth to insert Gated Clock manually in the Code or during BackEnd?

What cases are not covered by the Automatic Clock Insertion?

Thank you!

 

[harpv]

not sure I follow. modern CTS tools can pick up common enables and propagate them up in the tree with ICG cells.

That is true. Arch clock gates gives an option to switch off whole branches like what @George_P mentioned.