Clock Gating setup and hold time

[nschiku]

clock gating setup and hold checks

Hi,
Can anyone tell me how do we arrive at the setup and hold time values for clock gating checks?

Thanks,
Nik

 

[ljxpjpjljx]

clock gating setup hold timing

after you insert DFT scan ,you can do the check!

 

[Lixusan]

clock gating setup hold

About clock gating setup & hold check, different clock gating cell (such as AND, OR and NOR etc.) and different active edge of launch/gated clock will make this checking several combination. you can refer to the timing report and review your design to understand more and more. One article on solvnet is very helpful for you:
<<How Are Clock Gating Checks Inferred>>

 

[visualart]

what is clock gating check

You may margin the enough timig for the setup and hold, SO, the layout and STA can easy match the need of the library.

GOOD LUCKY

 

[navneetgupta]

clock gated setup checks

Hi...
I do not know much about it.....but as much i know is as follows.....

setup & hold time values required in this check are mainly the function of cells used in clock gating, it is not bad to say it is a functional of library you are using.

It also depends on our ckt....

hope it helps..................

regds
navneet