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[SOLVED] Clock Gating Insertion Problem

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coshy

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Dear All,

I've been trying to study a Clock Gating Insertion. So I've find good reference https://stackoverflow.com/questions/24977925/how-to-use-clock-gating-in-rtl/25003974#25003974
And, I've applied to my example code as the below


Code:
`define   RESET_STATE  3'b000
`define   FETCH_INSTR  3'b001
`define   READ_OPS     3'b010
`define   EXECUTE      3'b011
`define   WRITEBACK    3'b100

module TOP(Clk, Reset, Crnt_Instrn, Neg_Flag,  PC);
        input                   Clk;
        input                   Reset;
        input   [31:0]  Crnt_Instrn;            // Current Executing Inst
        input           Neg_Flag; // Flags from ALU or Stack
        output  [7:0]   PC;     // Program Count

        wire                    Ld_Brnch_Addr;

        wire            gclk;


        omsp_clock_gate u_omsp_clock_gate (
        // OUTPUTs
        .gclk    (    gclk        ),                      // Gated clock

        // INPUTs
        .clk    (    Clk        ),                       // Clock
        .enable    (    Neg_Flag        ),                    // Clock enable
        .scan_enable    (    1'b0)                // Scan enable (active during scan shifting)
        );

        COUNT   I_COUNT (
                .Reset(Reset),
                .Clk(gclk),
//                .Clk(Clk),
                .Imm_Addr(Crnt_Instrn[7:0]),
                .PC(PC)
        );

endmodule

module COUNT(Reset, Clk,  Imm_Addr, PC);
        input                   Reset, Clk  ;     // Reset for the PC
        input   [7:0]   Imm_Addr;  // Immediate Addr for Jmp/Call

        output  [7:0]   PC;     // Addr of instruction to be fetched in
                                // the next Fetch Cycle

        reg     [7:0]   PCint;

        always @(posedge Clk) begin
                if (Reset == 1'b1) begin
                        PCint   <= 8'b00000000;
                end else begin
                        PCint   <= Imm_Addr;
                end
        end


        assign  PC      = PCint;

endmodule



module  omsp_clock_gate (

// OUTPUTs
    gclk,                      // Gated clock

// INPUTs
    clk,                       // Clock
    enable,                    // Clock enable
    scan_enable                // Scan enable (active during scan shifting)
);

// OUTPUTs
//=========
output wire        gclk;           // Gated clock

// INPUTs
//=========
input          clk;            // Clock
input          enable;         // Clock enable
input          scan_enable;    // Scan enable (active during scan shifting)

///////////////////////////////////////////////////////////////////////////////////


wire    enable_in =   (enable | scan_enable);
assign gclk = enable_in & clk;

endmodule // omsp_clock_gate




and I Synthesis with SDC as below
Code:
reset_design
remove_design -all


alias
check_library

read_file -format verilog ./rtl/TOP.v
current_design TOP
link


current_design TOP

## Create clock object and set uncertainty
create_clock -period 2 [get_ports Clk]
set_clock_uncertainty 0.2 [get_clocks Clk]

## Set constraints on input ports
suppress_message UID-401
set_input_delay 0.1 -max -clock Clk [remove_from_collection [all_inputs] [get_ports Clk]]
set_input_delay 1.2 -max -clock Clk [get_ports Neg_Flag]

## Set constraints on output ports
set_output_delay 1 -max -clock Clk [all_outputs]

compile_ultra

report_constraint -all > ./report_constraint_all.rpt
report_timing -max_paths 100  > ./report_timing.rpt
report_area > ./report_area.rpt



I expect the synthesized gate netlist is as the below
2.PNG


But netlist compiled as the below
1613043988871.png


Even the Timing report also didn't show me any Clock-Gating relative Timing Report.


How To implement a Clock Gating methodology into gate netlist and got the Clock Gating Report in DC ? Does ICG cell inserting mean that using target library ICG cell?
 
Last edited:

ThisIsNotSam

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there is no need to insert clock gating at netlist level or code it in your RTL, the tools are smart enough to detect enable conditions from your code and insert CG automatically for you.
 

coshy

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there is no need to insert clock gating at netlist level or code it in your RTL, the tools are smart enough to detect enable conditions from your code and insert CG automatically for you.

Thank you Sir for replying.
I came across some lecture and articles.
http://classes.engineering.wustl.edu/ese461/Lecture/week12b.pdf
http://core.ac.uk/download/pdf/144449541.pdf
http://inst.eecs.berkeley.edu/~cs250/fa10/handouts/tut5-dc.pdf
http://core.ac.uk/download/pdf/144449541.pdf
http://venividiwiki.ee.virginia.edu/mediawiki/images/0/0c/F2012-Lec-11_Logic-Synthesis.pdf

So I added into my sdc file

Code:
set_clock_gating_registers -include_instances
[all_registers -clock "CLK"]
set_clock_gating_style -num_stages 2 -sequential_cell
latch -minimum_bitwidth 8 -max_fanout 32
insert_clock_gating –global
propagate_constraints -gate_clock

And I realized that there are 2 cases of purpose for clock gating.
One Clock Gating is for a clock(gating) and one Clock Gating is for a data(gating).

And I realized the following implement is for a clock (clock gating) not data

Code:
module TOP(Clk, Reset, Crnt_Instrn, Neg_Flag,  PC);
        input                   Clk;
        input                   Reset;
        input   [31:0]       Crnt_Instrn;            
        input                    Neg_Flag; 
        output  [7:0]       PC;     
        wire                       Ld_Brnch_Addr;
        wire                       gclk;                         // This is for Clock Gating
       
      assign gclk = Neg_Flag & Clk;           // This is for Clock Gating
        
       COUNT   I_COUNT (
                .Reset(Reset),
                .Clk(gclk),                                      // This is for Clock Gating
                .Imm_Addr(Crnt_Instrn[7:0]),
                .PC(PC)
        );
endmodule

And I got the below messages
Code:
Current clock gating style....
Sequential cell: latch
Minimum bank bitwidth: 1
Minimum bank bitwidth for enhanced clock gating: 2
Maximum fanout: 32
Setup time for clock gate: 0.000000
Hold time for clock gate: 0.000000
Clock gating circuitry (positive edge): and
Clock gating circuitry (negative edge): or
 Note: inverter between clock gating circuitry
       and (negative edge) register clock pin.
Control point insertion: none
Control signal for control point: scan_enable
Observation point insertion: false
Observation logic depth: 5
Maximum number of stages: 2
Warning: Clock gating insertion with insert_clock_gating is deprecated and will be removed in a fut
Information: Performing global clock-gating on design TOP

Clock Gate Insertion Report
===============================================================================
| Gated |                   | Include |      | Enable | Setup | Width | Clock |
| Group |  Flip-Flop Name   | Exclude | Bits | Cond.  | Cond. | Cond. | Gated |
===============================================================================
|       |                   |         |      |        |       |       |       |
|       |  GATED REGISTERS  |         |      |        |       |       |       |
|       |                   |         |      |        |       |       |       |
|       | UNGATED REGISTERS |         |      |        |       |       |       |
|       | I_COUNT/PCint_reg[0] |  -   |  1   |   no   |  ??   |  ??   |  no   |
|       | I_COUNT/PCint_reg[1] |  -   |  1   |   no   |  ??   |  ??   |  no   |
|       | I_COUNT/PCint_reg[2] |  -   |  1   |   no   |  ??   |  ??   |  no   |
|       | I_COUNT/PCint_reg[3] |  -   |  1   |   no   |  ??   |  ??   |  no   |
|       | I_COUNT/PCint_reg[4] |  -   |  1   |   no   |  ??   |  ??   |  no   |
|       | I_COUNT/PCint_reg[5] |  -   |  1   |   no   |  ??   |  ??   |  no   |
|       | I_COUNT/PCint_reg[6] |  -   |  1   |   no   |  ??   |  ??   |  no   |
|       | I_COUNT/PCint_reg[7] |  -   |  1   |   no   |  ??   |  ??   |  no   |
===============================================================================

Summary:
Flip-Flops                        Banks                   Bit-Width
                              number  percentage      number  percentage
Clock gated (total):             0            0          0            0
Clock not gated because
   Bank was excluded:            0            0          0            0
   Bank width too small:         0            0          0            0
   Enable condition not met:     1          100          8          100
   Setup condition violated:     0            0          0            0
Total:                           1          100          8          100
No clock gating opportunities were found.
Warning: Use of propagate_constraints -gate_clock is not recommended. This feature will be obsolete

#   Propagate Constraints from cell I_COUNT/ (COUNT) #

I've been trying to find for a while how to implement the clock gating but Couldn't it. If you don't mind, Would you please give me any clue for clock gating, how to insert Clock Gating into Netlist in SDC?
 

ThisIsNotSam

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you are missing the point. there is no need to do any of this, no SDC, no RTL modification. all you have to do is conditional logic in the most straightforward manner possible.


Code Verilog - [expand]
1
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3
4
5
reg [7:0] counter;
always@(posedge clk) begin
if (control = 1)
counter <= counter + 1;
end

 

coshy

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you are missing the point. there is no need to do any of this, no SDC, no RTL modification. all you have to do is conditional logic in the most straightforward manner possible.


Code Verilog - [expand]
1
2
3
4
always@(posedge clk) begin
if (clock_en= 1)
counter <= counter + 1;
end


Sir this gating is clock gating style as I understand. doesn't it?

but I want a clock itself gating. clock can't sample itself as I know so we need


Code Verilog - [expand]
1
2
3
4
5
reg [7:0] counter;
always@(posedge clk) begin
if (control = 1)
counter <= counter + 1;
end


you are missing the point. there is no need to do any of this, no SDC, no RTL modification. all you have to do is conditional logic in the most straightforward manner possible.


Code Verilog - [expand]
1
2
3
4
5
reg [7:0] counter;
always@(posedge clk) begin
if (control = 1)
counter <= counter + 1;
end


Thank you for reply Sir,
As I understand, the below gating style is data gated by clock.


Code Verilog - [expand]
1
2
3
4
5
reg [7:0] counter;
always@(posedge clk) begin
if (control = 1)
counter <= counter + 1;
end



But If I want a clock itself gating by using clock gating we can't sample the clock itself as the below. and also a tool doesn't understand whether the below code can be available a clock gating or not.


Code Verilog - [expand]
1
2
3
4
always@(posedge clk) begin
if (clock_enable= 1)
clk <= clk;
end

 

ThisIsNotSam

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I give up. You are creating a problem where there isn't one. Your understanding of what the tools can or cannot do is incorrect. Clock gating is fully automated for more than a decade.
 

oratie

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Let me help :)

You should have in RTL something like:

always (posedge CLK)
if (EN)
Q <= D ;

Then, use command
compile_ultra -gate_clock
 

coshy

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Let me help :)

You should have in RTL something like:

always (posedge CLK)
if (EN)
Q <= D ;

Then, use command
compile_ultra -gate_clock
Yes I know 'thisisnotsam' said that as your answer. But how about gating clock itself?
I want gating a clock not data.

because when I sameple the clock, The tool make error that user using clock as data.

clock clk used as data. (ELAB-305)
 
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oratie

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compile_ultra -gate_clock This command insert clock-gating cell in CLK path.

Did you understand option "-gate_clock" of compile_ultra command ? Did you try it with above RTL?
 

coshy

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compile_ultra -gate_clock This command insert clock-gating cell in CLK path.

Did you understand option "-gate_clock" of compile_ultra command ? Did you try it with above RTL?

Thank you. I found a Clock Gating register implemented by a Tool.
This is what I found it
1613316716895.png


In Clock Gating by Tool, That code need to be a Register style not combination style. And be implemented in synchronous clock domain not asynchronous.

But I want to know the gating of clock's itself gating.
I just draw the what I think the clock itself gating.

1613318384989.png

There are CLK, EN inputs and the output is CLK_EN signal which is controlled by EN as Gating signal. The Gating Signal is going to spread to the system.

Is this called as a Clock Gating? If Yes, How To implement this ? By Tool? Manually? This is different style what I've done with clock gating by tool automatically.

If you don't mind Could you please let me know about this?
--- Updated ---

I give up. You are creating a problem where there isn't one. Your understanding of what the tools can or cannot do is incorrect. Clock gating is fully automated for more than a decade.
Sorry But I think Almost there. Sorry again for my foolish.
 

oratie

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If -gate_clock option is not what you want, you can manually insert clock gating library cell (not the gating code) directly in RTL. And set_dont_touch on it before compile.
 

coshy

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For someone who have the same question. I would a update.

dc.tcl

Code:
# This file has been edited to keep it simple
reset_design
remove_design -all

#source common_setup.tcl
#source dc_setup.tcl

#printvar target_library
#printvar link_library
alias
check_library
#check_tlu_plus_files
read_file -format verilog ./rtl/TOP.v
current_design TOP
link
write -hierarchy -f ddc -out ./unmapped_TOP.ddc
write -f verilog -hierarchy -output unmapped.v
list_designs
list_libs

#set_clock_gating_registers -include_instances [all_registers -clock "Clk"]


source ./scripts/TOP.con
replace_clock_gates
# Need to num_stages > 1 to see all implemented clock gating
set_clock_gating_style  -num_stages 4 -setup 0.5

#replace_clock_gates
compile_ultra -gate_clock -no_autoungroup

set_clock_gating_check -setup 0.0
write -f verilog -hierarchy -output mapped.v
report_constraint -all > ./report_constraint_all.rpt
report_timing -max_paths 100  > ./report_timing.rpt
report_area > ./report_area.rpt
write -hierarchy -format ddc -output ./mapped_TOP.ddc
#remove_design -all

TOP.con
Code:
current_design TOP

## Reset all constraints
#reset_design

## Create clock object and set uncertainty
create_clock -period 2 [get_ports Clk]
set_clock_uncertainty 0.2 [get_clocks Clk]

## Set constraints on input ports
suppress_message UID-401
#set_driving_cell -library $lib_name -lib_cell sdcfq1 [remove_from_collection [all_inputs] [get_ports Clk]]
set_input_delay 0.1 -max -clock Clk [remove_from_collection [all_inputs] [get_ports Clk]]
set_input_delay 1.2 -max -clock Clk [get_ports Clk]
set_input_delay 1.2 -max -clock Clk [get_ports Reset]
set_input_delay 1.2 -max -clock Clk [get_ports Crnt_Instrn]
set_input_delay 1.2 -max -clock Clk [get_ports Clock_Flag]

## Set constraints on output ports
set_output_delay 1 -max -clock Clk [all_outputs]
set_load [expr [load_of $lib_name/an02d0/A1] * 15] [all_outputs]

TOP.v

Code:
`define   RESET_STATE  3'b000
`define   FETCH_INSTR  3'b001
`define   READ_OPS     3'b010
`define   EXECUTE      3'b011
`define   WRITEBACK    3'b100





module TOP(Clk, Reset, Crnt_Instrn, Clock_Flag,  PC);
        input                   Clk;
        input                   Reset;
        input   [31:0]          Crnt_Instrn;  
        input                      Clock_Flag;
        output  [7:0]              PC;  

        wire                    Ld_Brnch_Addr;

        wire                    g_clk;
        reg                     enable_flop;



        always@(negedge Clk)
          enable_flop <= Clock_Flag ; //This is for Clock Gating Test. This is Manual So I used a replace_clock_gates

        assign g_clk = Clk & enable_flop;

        COUNT   I_COUNT (
                .Reset(Reset),
                .Clk(g_clk),
                .control(Crnt_Instrn[0]),
                .PC(PC)
        );


endmodule

module COUNT(Reset, Clk,  control, PC);
        input           Reset, Clk  ;  
        input           control;
        output  [7:0]   PC;
        reg     [7:0]   PCint;


        always @(posedge Clk) begin
                if (Reset == 1'b1)
                        PCint   <= 8'b00000000;
                if (control == 1)                     // This is for Clock Gating Test
                        PCint   <= PCint + 1;
        end
        assign  PC      = PCint;

endmodule
 

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