There is a register in a pipelined data path implementation. If the register's clock is gated can it retain its value? or else I have to move that value to some other register whose clock is not gated..........
a flop is designed to retain the value on the Q output until the next clock edge. If D is different than Q, then Q will change. If you don't give the flop another clock edge, then Q will stay the same ...
The clock gating of synthesis tool operates in the following manner........ If say the tool finds the following structure in the design
then if S=0 same data will be saved in flop and if S=1 new data can be loaded in the flop, thus when S=0 the clock reaching the FF can be gated so the synthesis tool will put a clock gate in the clock path and put its enable as S'. In fact tool will group the flops which will have same scenario (ie: same enable) and will use a common clock gate for all these flops.
Further in this question, can any body tell in case of gated cell for clock, which constraint has to give for gated enable pin, for synthesis and Timing Analysis???