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[Clock Gating] Clock gating enable and disable.

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maulin sheth

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Hello ALL,

How to enable the functional enable signal of Clock gating?
If, I have to insert clock gating logic into design, thn How to decide to make connection of functional enable signal of Clock gating cell?
What are the constraints/dependancies for functional enable signal?

Thanks in advance.

Thanks & Regards,
Maulin Sheth
 

rca

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When you insert the clock gating manually, you move the gating signal currently used on data path to the clock path.
So you used the "old" data gating signal as clock gating signal, and you could removed the data gating after been used as clock gating.
 

ramesh28

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Hi rca,

When you insert the clock gating manually, you move the gating signal currently used on data path to the clock path.
So you used the "old" data gating signal as clock gating signal, and you could removed the data gating after been used as clock gating.

can you explain this in detail?

I want to know how we handle enable signal in clock gating means (on/off)? and how to genetare enable signal from where?
 

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