jaya sree
Member level 3
hai everyone ,
in my project , there are some clock gating violations starting from input port and ending at clock gating cell pin.However ,there is guidance to ingnore these type of violations. Why these violations must be ignored? Are these false violations ? or will these be taken care by PDI ( full chip )
Startpoint: [ MODERATOR - CODE DELETED AT USER REQUEST]
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data required time 33.286
data arrival time -33.651
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slack (VIOLATED) -0.365
in my project , there are some clock gating violations starting from input port and ending at clock gating cell pin.However ,there is guidance to ingnore these type of violations. Why these violations must be ignored? Are these false violations ? or will these be taken care by PDI ( full chip )
Startpoint: [ MODERATOR - CODE DELETED AT USER REQUEST]
------------------------------------------------------------------------------------------------------------------------------------------------------
data required time 33.286
data arrival time -33.651
------------------------------------------------------------------------------------------------------------------------------------------------------
slack (VIOLATED) -0.365