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clock gating check ( setup)

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jaya sree

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hai everyone ,


in my project , there are some clock gating violations starting from input port and ending at clock gating cell pin.However ,there is guidance to ingnore these type of violations. Why these violations must be ignored? Are these false violations ? or will these be taken care by PDI ( full chip )


Startpoint: [ MODERATOR - CODE DELETED AT USER REQUEST]
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data required time 33.286
data arrival time -33.651
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slack (VIOLATED) -0.365
 

pavanks

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I guess coz the violation is very small and can be fixed in the later stage of the design. They might have told u to ignore for now.

Or it might that there is enough margin already given on this so this is okay.
 

jeevan.life

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clock gating setup check is used to ensure the controlling data signals are stable before the clock is active. This check is performed on combinational gates through which the clock signals are propagated. The arrival time of the leading edge of the clock pin is checked against both levels of any data signals gating the clock. A clock gating setup failure can cause either a glitch at the leading edge of the clock pulse, or a clipped clock pulse
 
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