Clock Gating Check in STA

[atlaakreddy]

1) I am new to STA. I know that Clock gating is used to save the Switching Power by shutting down the clocks to the registers when not needed. But if there is an inverter in the gated clock signal just before it reaches the sink pin of the registers, the inverter will turn the clock signal to be high and so the register will be ON eventually. How does clock gating saves the power in this case?

2) Also how come we identify an aggressor net based upon Drive Strength, Frequency and voltage?

3) Will there be any crosstalk between 2 nets if they have same voltage and different drive strength?

I am seeking a clear explanation with an example.

Thank you all.

 

[ThisIsNotSam]

1) clock gating implementation takes care of that. There typically is an enable signal that is ended with the clock signal, so the scenario you propose doesn't really happen. STA is clock gating aware.

2-3) yes. crosstalk does not depend only on voltage levels and strength, the actual transition matters.