I am using encounter for PR, and in the design there are many clock gating cells that are implemented with " LATCH+ AND" gates.
After PR, I found that the LATCH and AND gates are separated far away, like 100um. Is there any way in encounter to restrict the distance between them?
usually the technology library come with the standard cell for clock gating. You can use that so that you don't have to worry about placement of latch and AND.