shaiko
Advanced Member level 5
Hello,
I have an FPGA clock coming into my design.
I want to simply send this clock using another pin.
From working with Xilinx - I learned that the recommended practice is to use an Output DDR Flip Flop for that purpose - as described in this link :
http://forums.xilinx.com/t5/Timing-Analysis/Why-ODDR-for-forwarded-clock/td-p/756737
Is this also the recommended practice for Intel FPGAs ?
I have an FPGA clock coming into my design.
I want to simply send this clock using another pin.
From working with Xilinx - I learned that the recommended practice is to use an Output DDR Flip Flop for that purpose - as described in this link :
http://forums.xilinx.com/t5/Timing-Analysis/Why-ODDR-for-forwarded-clock/td-p/756737
Is this also the recommended practice for Intel FPGAs ?