3/5 could be considered, but there will be edges that are not lined up, but also near in time to each other. Most developers would treat these as different because they would use async fifo's, synchronizers, etc... to ensure reliable signal crossings -- they would be treated as unrelated from a design standpoint. If the clock is low enough, timing could still be met, and you could consider them to be the same domain.
You could also track cycles and ensure the edges will align when data is transferred between the registers of the different clocks.
A common example for different clock domains would be serial communications. Both sides might have a 156.25MHz clock generated from a different source. The clocks can vary slightly over time, temperature, etc... So even though they are intended to be the same frequency, they are not exactly the same frequency. The result is clock edges near, but not aligned to each other. This means a register might update in one domain, logic might start to change, then the some mixture of correct and incorrect data will be registered in the other domain.