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Clock domain crossing

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sakshi gupta

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1.How we can distinguish between data & control crossings ?

2. Which type of synchronisation scheme should be used for
a. data crossings
b. control crossings :?:
 

Now it depends,whether its a control or data signal,
if its okay to lose data then u pass it through synchronizer,
& if design says not to lose data or control signal then u need to go for a FIFO.

suppose if its streaming video or text.then its ok to lose,but if its text file then u just cant skip a bit.:grin:

---------- Post added at 10:22 ---------- Previous post was at 10:21 ----------

Now it depends,whether its a control or data signal,
if its okay to lose data then u pass it through synchronizer,
& if design says not to lose data or control signal then u need to go for a FIFO.

suppose if its streaming video or text.then its ok to lose,but if its text file then u just cant skip a bit.:grin:

mistake at last line...not text after video..
 

usually we will have some method for cross-clock domain : 2 flip-flop sync, gray code , async handshake ! you can try run!
 

Actually, the difference between control and data is that control signals are usually single bit and data signals are usually multi-bit bus. To make bus to cross clock domain, the flip flops can't be used. Why? because, for example, a data is 4 bits wide, and it goes from 0000 -> 0011 before clock domain crossing. Due to the slight difference of timing among the bits, the data in new clock domain will be 0000 -> 0001 -> 0011. In other words, a new data is generated. This is not allowed in many applications. That is why FIFO is recommended.
 

Actually, the difference between control and data is that control signals are usually single bit and data signals are usually multi-bit bus.

I don't agree control signal are usually single bit . Control signals can be multibit . In case of multibit control signals , if we are using multiflop synchronization scheme ,we need to gray encode the data to avoid data coherency issues .
 

Use of gray code is limited to very specific application,and it doesn't solve majority of the problem in clock domain crossing. All you need is handshaking where the multi bit stuffs are all stable when they get captured.
 

I mean to say :
1) Control crossings-
we can synchronise by Double FF only if data is gray encoded . We can also use FIFO & handshake for control crossings in design

2) Data bus crossings
We can use Recirculation mux, synchronized enable techniquies .
 

I mean to say :
1) Control crossings-
we can synchronise by Double FF only if data is gray encoded ..

That's not how the thing works in reality. Gray code works only if you know the data sequence like the pointer in the FIFO, which isn't the case in most of the control signals. You can't gray code some random multibit control signals to force the a single bit change at a time. Real life operation in domain crossing is most of the control signals are sent as well as data in advance and only 1 bit deferred signal triggers the transaction. If you want to send the random multiple control signals with the data all together, you have to use FIFO.

Synchronization is just to avoid the metastability and it is required regardless of a single bit or multi bits or control or data when crossing the clock domain where the phase relation is not locked.
 
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May I ask the question - if data is gray encoded, can we also use double FF?

The point here is that there is really no difference between data and control signals when we discuss clock domain crossing. The difference exists in the ways we deal with single bit and multi-bit signals when they cross clock domain.
 

Real life operation in domain crossing is most of the control signals are sent as well as data in advance and only 1 bit deferred signal triggers the transaction. .

Can you explain this in more detail ?

---------- Post added at 07:21 ---------- Previous post was at 07:12 ----------

May I ask the question - if data is gray encoded, can we also use double FF?

.

Yes, you can use double Flop is data is gray encoded . This is to avoid data coherency issues .
It might be possible due to different delays in different synchroniser paths , you might get corrupted value . This is just to ensure only one bit of data changes at one time . this is mostly used for control signals as in case of FIFo pointers .
 

just a typical handshake, where r/w, addr, data and so on are sent to the receiving block a few cycles before the request signal is sent and the sender holds them. A few cycle later that r/w, addr, data or such are presumably stable, request signal is sent and it triggers the receving block to capture the data, r/w, addr.
 

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