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clock domain crossing

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ASIC_intl

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when can we use two flops as synchronizer (for one bit control signal) for the frequency of the sending domain is higher than the receiving domain or the reverse of that?
 

jbeniston

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So long as the frequency of the control signal itself isn't higher than the frequency of the receiving clock domain, you should be ok. i.e. if the control signal is only asserted for one faster clock cycle, it could be missed.
 

speedforu

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signal crossing from slower clk domain to faster clk domain needs more flip flops for synchronization, as the time to settle to stable value from meta stable value in the case of faster clk is less and hence it may be necessary to put more flops in the synchronizer. But as Nir Dahan said, it depends frequencies and also the technology parameters.
 

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