am85
Member level 2
Hi,
We are connecting a 100Mbit Ethernet PHY to an FPGA via RMII. We wanted to connect it the RMII interface to the FPGA transceiver (Altera TSE with PCS + PMA only) to send the data via SGMII to another device, so we have an RMII to MII converter since TSE has no RMII interface. The Converter uses the same 50 MHz clock as the PHY and converts between the 4-bit MII and 2-bit RMII. However, the FPGA transceiver has a clock of 125 MHz and a 25 MHz clock enable signal in MII mode.
Are clock domain crossing techniques required here? and which one would fit the best ?
Thanks.
We are connecting a 100Mbit Ethernet PHY to an FPGA via RMII. We wanted to connect it the RMII interface to the FPGA transceiver (Altera TSE with PCS + PMA only) to send the data via SGMII to another device, so we have an RMII to MII converter since TSE has no RMII interface. The Converter uses the same 50 MHz clock as the PHY and converts between the 4-bit MII and 2-bit RMII. However, the FPGA transceiver has a clock of 125 MHz and a 25 MHz clock enable signal in MII mode.
Are clock domain crossing techniques required here? and which one would fit the best ?
Thanks.
