Mark Baseggio
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Hello,
I am working on building a homebrew computer, when learned about bus decoding I decided that it would be awesome to learn PLD in the process. And so here I am. I've got the Dangerous Prototypes CPLD breakout, and the Mojo v3 from Embedded Micro (with a Spartan 6). Currently I'm prototyping with it because it has a 50Mhz clock on the board and the CPLD doesn't.
After some Googling and searching on this forum I have a basic 1Mhz clock divider working, or so it appears according to my Saleae Logic probe. This small feat has me excited for the opportunities and plans I have for this computer.
I was hoping that a few people could take a gander at my clock divider code and provide some feedback, because I'm not sure if I'm doing it the best or "proper" way. Also, as the topic says I plan on integrating a few buttons: one to stop the clock (note it must be stopped HIGH to prevent memory loss on the 6502), and another to then single step the CPU one clock cycle at a time (always stopping high for reasons already mentioned).
If anyone feels like providing suggestions I'd be grateful! Here's the code:
in my constraints file I also had to add the following:
And the result, YAY it works (I know, this is simple stuff, but give me a break, baby steps here!)
Oh and one last thing. Eventually I will also be needing a 20Mhz clock to communicate with a SPI SRAM that I will be adding. Would it be advisable to generate both signals in the same module?
Thanks for reading!
I am working on building a homebrew computer, when learned about bus decoding I decided that it would be awesome to learn PLD in the process. And so here I am. I've got the Dangerous Prototypes CPLD breakout, and the Mojo v3 from Embedded Micro (with a Spartan 6). Currently I'm prototyping with it because it has a 50Mhz clock on the board and the CPLD doesn't.
After some Googling and searching on this forum I have a basic 1Mhz clock divider working, or so it appears according to my Saleae Logic probe. This small feat has me excited for the opportunities and plans I have for this computer.
I was hoping that a few people could take a gander at my clock divider code and provide some feedback, because I'm not sure if I'm doing it the best or "proper" way. Also, as the topic says I plan on integrating a few buttons: one to stop the clock (note it must be stopped HIGH to prevent memory loss on the 6502), and another to then single step the CPU one clock cycle at a time (always stopping high for reasons already mentioned).
If anyone feels like providing suggestions I'd be grateful! Here's the code:
Code:
module clock_div(
input clk,
input rst,
output mpu_clk
);
parameter period = 50;
parameter halfperiod = 25;
reg mpu_clk;
wire rst,clk;
reg [5:0] countvalue;
always @(posedge clk) begin
if(rst) begin
countvalue <= 5'b0;
mpu_clk <= 1'b0;
end
else begin
if(countvalue == period - 1'b1) begin
countvalue <= 1'b0;
mpu_clk <= 1'b0;
end
else countvalue <= countvalue + 1'b1;
if(countvalue == halfperiod) mpu_clk <= 1'b1;
end
end
endmodule
in my constraints file I also had to add the following:
Code:
NET "mpu_clk" LOC = P1;
And the result, YAY it works (I know, this is simple stuff, but give me a break, baby steps here!)
Oh and one last thing. Eventually I will also be needing a 20Mhz clock to communicate with a SPI SRAM that I will be adding. Would it be advisable to generate both signals in the same module?
Thanks for reading!
Last edited: