Clock Divider from 921600Hz to 115200Hz

module step1_divider (
input clki,
input reset,
output reg clkf
);

localparam constantNumber = 4'b1000;
reg [3:0] count;
 

always @ (posedge(clki) or posedge(reset))
begin
    if (reset == 1'b1)
		  begin
		  count <=4'b0;
        clkf <= 1'b0;
		  end
    else
	 begin 
	 if(count == 4'b0)
	 clkf <= 1'b1;
	 if (count == 4'b0100)
	 clkf <= 1'b0;
	 if (count == constantNumber)
	 count <= 4'b0;
	 count <= count +1;
	end	
end
endmodule

always @ (posedge(clki) or posedge(reset))
begin
    if (reset == 1'b1) begin
        count <=4'b0;
        clkf <= 1'b0;
    end else begin 
        if(count == 4'b0) begin
            clkf <= 1'b1;
        end
        // missing "else", but the condition won't be reached when count == 0
        if (count == 4'b0100) begin
            clkf <= 1'b0;
        end

        if (count == constantNumber) begin
            count <= 4'b0;
        end
        // missing else, this statement is always reached and thus the only one that matters.
        count <= count +1;
    end	
end