Nov 24, 2019 #1 P promach Advanced Member level 4 Joined Feb 22, 2016 Messages 1,199 Helped 2 Reputation 4 Reaction score 5 Trophy points 1,318 Activity points 11,636 How is https://www.academia.edu/9005130/DE...DISTRIBUTION_CIRCUIT_USING_SINGLE_PHASE_CLOCK different compared to clock divider tutorial at https://zipcpu.com/blog/2017/06/02/generating-timing.html ? One is using TSPC prescaler approach in CMOS gates ? The other is using counter approach in verilog ? Last edited: Nov 24, 2019
How is https://www.academia.edu/9005130/DE...DISTRIBUTION_CIRCUIT_USING_SINGLE_PHASE_CLOCK different compared to clock divider tutorial at https://zipcpu.com/blog/2017/06/02/generating-timing.html ? One is using TSPC prescaler approach in CMOS gates ? The other is using counter approach in verilog ?
Nov 25, 2019 #2 dpaul Advanced Member level 5 Joined Jan 16, 2008 Messages 1,799 Helped 317 Reputation 635 Reaction score 342 Trophy points 1,373 Location Germany Activity points 13,071 Don't know about the first. The other one is the form widely used within digital designs. Depends on what you are trying to do.
Don't know about the first. The other one is the form widely used within digital designs. Depends on what you are trying to do.
Nov 25, 2019 #3 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,548 Helped 397 Reputation 794 Reaction score 463 Trophy points 1,363 Activity points 14,760 the first is a PLL design from unknown researchers in a meaningless journal. validated with simulation (sigh) the second is something that works reliably and is utilized very often
the first is a PLL design from unknown researchers in a meaningless journal. validated with simulation (sigh) the second is something that works reliably and is utilized very often