Clock divider by 3/7 -> how to implement?

[ivlsi]

Hi All,

How to implement a clock divider by 3/7? There should be a special formula, does anybody know?

Thank you!

 

[FvM]

The factor three involves a frequency multiplication, isn't it? In so far it's no simple frequency divider.

Is a fractional divider an option?

 

[sharath666]

A precise combination of invertors & buffers should yield the result. But managing such a clock tree will be very tough. I won't recommend it.

 

[ivlsi]

Is a fractional divider an option?

Exactly! How to implement it?

 

[FvM]

Make a modular adder accu = (accu + 3) mod 7
Generate clock pulse in case of overflow

 

[ivlsi]

Make a modular adder accu = (accu + 3) mod 7
Generate clock pulse in case of overflow

Thanks! This is the way how to create the 3/7 clock period. But how to create 50% duty cycle (or another DC, which is as close to 50% as possible)?

 

[FvM]

50 % duty cycle isn't possible. Please consider that the fractional divider output period is jittering between 2 and 3 input clock cycles. Only a PLL clock generator can avoid these drawbacks.

 

[ivlsi]

fractional divider output period is jittering between 2 and 3 input clock cycles

Can you explain this please? Why between 2 and 3 input clock cycles? What's special in the cycle#2 and cycle#3?

 

[FvM]

Because 7/3 = 2.33

 

[ads-ee]

Here is a picture of how you would have to do this 2.33 ratio clock output to have the 3/7 frequency division:

[FONT=Courier New]   __    __    __    __    __    __    __    __    __
__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__
   _____       _____       _____             _____
__|     |_____|     |_____|     |___________|     |_____

  |---- 2 ----|---- 2 ----|------- 3 -------|[/FONT]

As you can see the duty cycle has jitter due to the 3 clock cycle period for one of the three clock edges.