Clock distribution and power routing

[spartacus2]

clock and power routing

If the power and ground line is routed close to the clock distribution circuitry, what can be the effects?

Added after 3 minutes:


Its effects on noise margin, system performance...etc??? I don't have proper answers to these.

 

[rakeshnunna]

high frequency power routing

In general for high frequency designs we route the clock nets close to the power or ground nets to shield the clock tree from unwanted crosstalk effects.

 

[spartacus2]

But what effects does clock switching have on power rails? I would love to know how effects affect the noise margin, skew and performance.

 

[Ken Taylor]

If your power nets are substantial enough, such as in a plane rather than just a trace, the effect should be minimal and is the generally preferred method of distribution. However at the switching device (the clock generator chip, etc) there needs to be reservoir capacitor(s) on the power supply to prevent noise caused by inability to provide the transient currents at switch-on. Again this is also a function of supply net dimensioning.

 

[mubeen630]

Ground plane is recommeded to shield clock traces when going from the clock generator IC to the reciever(stripline topology). Ground pouring can be control with respect to clock trace width inorder to reduce the skew and reduce the parasitic capacitance. like for 4mil clock trace move ground away 6mils all around. essentially providing a coax effect.

As Ken descibed, Power can also be used as a reference plane to shield the clock but preference is given to the same supply level as the voltage of clock so that return current has the same reference as the cmos switch (clock generator IC).

In a system where several voltages are used ground should be prefered. where power is run as thick traces rather than planes.

Also, it is not recommeded to run clock traces close to any power supply traces due to strong coupling.

 

[laglead]

It will increase the loading of clock net due to the side-wall parasitic cap between metal lines.

 

[mubeen630]

In order to avoid this you can increase the distance of clock net from groun plane and guard traces. This keeps the clock isolated from contaminating other signals and keep the parasitic capacitance low.