clock constraint in DC

[rsrinivas]

Hi all
I have a design with some 13 modules and the controller controls the 12 modules.
I have synthesised the netlist and is working fine but now my problem is like this
The inputs to the controller are clk and reset.
from the clk input to the controller the controller generates clk to all the modules.
The maximum operating speed of my core(1 module) was 100 MHz but when i
use all the modules the speed of operation goes beyond 300 Mhz.
this may be because DC has to be given directives like there are generated clk's in the design
now how do i solve this.
pls help

cheers
srinivas

 

[spauls]

rsrinivas ,
Its better to do synthesis with high clock frequency and then analyze design timing margin.

 

[satya_422]

Hi, If your clear at one module working at 300Mhz , I can Help you.

IF you have each module opeating at different speeds , You should consider Clock control unit as a clock generation block.

U can do in the following way, Assign the clock to individual blocks and respective clock, Later u integrate according to the requirements you constrain generated clock.
IF ur more clear abt the question I will help u more..

--satya