clock cannot pass gating cell

[herezt]

hi,
my DC/PT check_timing report said that there are unconstrainted pathes in the design. After I checked the pathes, I found that some registers behind a gating cell is not constrainted. clock does not pass the gating cell which is generated during synthesis. Cound some tell me why this happens?
The EN pin of clock gating cell is not constant. It toggles in gate level simulation.
There are other clock gating cells in the design. Clocks pass them correctly.
Thanks.

 

[viswanadh_babu]

Hi ,

Please check the cell definition of this cell in library .
The clock pin should have a is_clock_true attribute and cell should have an attribute like "clock_gating_integrated_cell"

Only then the tool will propagate clock
Hope this helps

Regards,
K.VISWANADH BABU

 

[herezt]

hi, viswanadh_babu
Thanks for your guide. is_clock_pin of the CK pin of this cell is false. I look into the libraray description, CK pin has clock attribute. And CK pin of other good cells have this attribute ture. Why the is_clock_pin of this cell is lost?

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I try to set this attribute to ture for this cell pin but failed. It says it can not be set with set_attribute command.