clock buffers in data path

[jaya sree]

hai everyone,

in my design , i am seeing clock buffers of drive strength 6ur in data path.The path is from register output ( Q pin) to clock gate input (E pin) .As far as i know , clock buffers must not be used in data path as they consume more power and may act as aggressor . Is this a problem . Is there any case where clock buffers and inverters are used in data path.I got to know that if fanout is more i.e > 20 in data path , then sometimes we use clock buffers. Is this true? please help me

 

[Alosevskoy]

Is there any case where clock buffers and inverters are used in data path.

For example, inverters can be used in the datapath to fix hold violations..

 

[jaya sree]

u mean clock inverters will be used in data path ? normal inverters can also be used right ?

 

[yadavvlsi]

If you don't specify clock buffers and inverters as don't use, they can be used in data path also. Tool doesn't know whether a buffer is clock buffer or normal buffer. You can avoid use of clock buffers and inverters in data path by putting don't use on them during optimization.

 

[jeevan.life]

If you don't specify clock buffers and inverters as don't use, they can be used in data path also. Tool doesn't know whether a buffer is clock buffer or normal buffer. You can avoid use of clock buffers and inverters in data path by putting don't use on them during optimization.

You need to hide the clock buffers and invertors before CTS and then un hide them during CTS. This should solve your issue.

 

[yadavvlsi]

@Jeevan.life: Buffer list for CTS is taken from clock specification file. So always keep don't use on clock buffer and inverters.

 

[jeevan.life]

@Yadav: Thanks for the suggestion. I used to follow the process I mentioned above and add the clock buffer and inverter list in the clock specification file.