Hello EDA fellows.
I want to ask you something about clock driving for my 1uF flying capacitor. I'm making my LED driver IC now and my problem is how can I drive my 1uF external capacitor with my internally produced 1MHz clock. I'm afraid taper buffer would be very very large if I'm going to use it.
Calculation is simple: I = 2fC*δV (factor of 2 , because you have only about half the clock cycle time for loading; δV is C's ripple). So with f=1e6 and C=1e-6 you get twice the voltage ripple as current. No pb. with milliVolts of ripple, but surely if you have to reload hundreds of milliVolts per cycle.
Hello Sir, Erikl...
Thank you very much for your reply..
I'm so sorry but I can't relate to your computation for the current. My concern is this, Is there any other option of clock buffer aside from the taper buffer that I could used for my internally produced clock pulses. I already have the circuit of the clock pulse generator and it works fine.
---------- Post added at 15:39 ---------- Previous post was at 15:34 ----------
Is the computed current is the amount of current that would flow through the inverter of the last stage of the taper buffer?
Neither do I know your process nor the clock buffers of your library, sorry! But if the biggest one isn't big enough, you could probably use a few of them in parallel (use multiplicity factor m).
the clock before without any buffer or load produced 1MHz. However, when the clock is connected to the pump through a 10 stages taper buffer the resulting frequency is not the same. I can't understand what just happened.
Sometimes HSPICE shows internal timestep error, like internal timestep is too small. It is caused by convergence problem. You can try other simulator like Spectre.
Spectre's convergence is much better than HSPICE.
Sometimes HSPICE shows internal timestep error, like internal timestep is too small. It is caused by convergence problem. You can try other simulator like Spectre.
Spectre's convergence is much better than HSPICE.
I checked your waveform again. The first waveform shows another problem: The rising edge is much slow than falling edge. So driving capability in the buffer should be increased for this edge.
I checked your waveform again. The first waveform shows another problem: The rising edge is much slow than falling edge. So driving capability in the buffer should be increased for this edge.