Clock Balancing for cross-clock domains

[subbu.pv]

Hi All,
We usually specify the Max latency and the Max skew in the clock spec file for individual clocks and synthesize them separately in a multi clock domain designs.
But if there are cross-clock domains, where in data is flowing from one clock domain to other clock domain, then both the clock needs balancing. So what are the inputs we give during CTS stage, So that the tool balances the Skew between those two clock domains ?
Can someone help me with this ?

 

[matter]

Hi Subbu,
In future, please state the tool name when your ask for tool specific help. How can anyone read your mind to figure out if you are using Synopsys, Cadence or some other eda tool ?

I am going to assume that you are using Synopsys ICC. In ICC, you can use "set_inter_clock_delay_balance_options" command to balance clock networks. Please read man page for this command for further details.

Regards