Clk synchronization in Pipeline ADC

[mahshidkardan]

Hi,

I have designed a 10-bit pipeline ADC and now I am trying to arrange gain stages around the clk generator(on the layout) in a way that the stages which should be synchronized, receive the clk at the same time. I do not know how much latency causes the distance between clk and gain stages on the layout and if this distance can affect the clk synchronization or not. I did not find any document on the web related to this problem. Would you please let me know about it if you have any information or references?

Thank you in advance

 

[shanmei]

Or you can use a metal layout to do post-sim to get the delay.

 

[mahshidkardan]

Thank you for your note. Actually I know how I can simulate it. But I can not find any reference or publication about how the layout distances can affect the clk synchronization on Pipeline ADC and if there is any solution or arrangement for it. Do you know any related document?

 

[shanmei]

sorry. I do not know.

 

[NiedeLu]

As in every transmission line the frequency of your clock is the major indicator how much delay is acceptable.

Here you can find a paper where the delay for a 400MHz clock is modeled: https://www.ece.ucsb.edu/bears/class/ece124d/IBM_clock2.pdf

BR
Lukas