sinclair.ahmd
Newbie level 3
hello,
i m working on msp430f5529 processor just i m getting problem in setting clock .
here is my clock setting. but my problem is whenever i do some changes my timer in working.
"
thank you in advance .
Please help me in this clock initialization i m totally confused.
i m working on msp430f5529 processor just i m getting problem in setting clock .
here is my clock setting. but my problem is whenever i do some changes my timer in working.
Code:
UCSCTL3|= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_6; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz
UCSCTL3 |= SELREF_2; // (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0);// Enable the FLL control loop
/* Worst-case settling time for the DCO when the DCO range bits have been changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx UG for optimization. 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle */
__delay_cycles(375000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // bit XT1HFOFFG of register UCSCTL7 is not available in MSP430F5529 // Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
TA0CCTL0 = CCIE; // CCR0 interrupt enabled
TA0CCR0 = 40000; // Display timer - for 32mS - 32K@8MHz, 4K@1MHz - currently SMCLK used
TA0CTL = TASSEL_2 + MC_2 + TACLR + ID__8 ;
thank you in advance .
Please help me in this clock initialization i m totally confused.
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