clk divide hardware count

[sp]

i write the VHDL clk divide code... and i hav some doubt on it... hope someone can help me...

my question is like tht.... the code is as follow...

library ieee;
use ieee.std_logic_1164.all;
 
entity clk_div is
  generic(N: positive:= 2);
  port
    (fast_clk, reset: in std_logic;
     slow_clk: buffer std_logic
    );
end clk_div;
 
architecture behavioural of clk_div is
begin
  process(reset, fast_clk)
    variable count: natural;
  begin
    if reset = '1' then
       count := 0;
       slow_clk <= '0';
    elsif rising_edge(fast_clk) then
       count := count + 1;
          if count = N then
             slow_clk <= not slow_clk;
             count := 0;
          end if;
   end if;
  end process;
end behavioural;

and everytime i run compilation using the different N the hardware used on my FPGA doesnt change... i tot changing N would increase the counter flip flop used... doesnt it?....i used N = 2 and N = 25Mega... the hardware used also is the same...

wad actually is the hardware used to divide the clock?.... flip flops?...counter??
the hardware resources used is shown bellow... all N wth the same resources used...

my regards,
sp

 

[nand_gates]

Whatever results ur geting are correct! What ur are parameterising is just
the compare value and not the number of counter flops! What I mean is, for
counter you have define "variable counter : natural;" This will syntesize to
a 32 bit counter for any value of N!! Thats why you are getting the same
hardware for any N.
To solve this you define conter as follows!
variable counter : std_logic_vector((logto the base 2 of N) downto 0);

Here you need a function to calculate log to the base 2.
Checkout the follwing modified code!

Hope this helps!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk_div is
  generic(N          :        positive := 10);
  port
    (fast_clk, reset : in     std_logic;
     slow_clk        : buffer std_logic
     );
end clk_div;

architecture behavioural of clk_div is
  function log ( n : integer) return integer is
    variable i : integer := 1;
    variable j : integer := 2;
  begin  -- log
    while (n - j > 0) loop
      j := j*2;
      i := i + 1;
    end loop;
    return i;
  end log;
begin
  process(reset, fast_clk)
    variable count : std_logic_vector((log(N)-1) downto 0);
  begin
    if reset = '1' then
      count      := (others => '0');
      slow_clk   <= '0';
    elsif rising_edge(fast_clk) then
      count      := count + 1;
      if count = N then
        slow_clk <= not slow_clk;
        count    := (others => '0') ;
      end if;
    end if;
  end process;
end behavioural;

 

[sp]

is there any error on the last IF statement??....

if count = N then
        slow_clk <= not slow_clk;
        count    := (others => '0') ;
      end if; then
        slow_clk <= not slow_clk;
        count    := (others => '0') ;
      end if;

the "if count = N then" should be "if count = log(N) then"

am i correct... count cannot b compare to N... not the same type...


regards,
sp

-------------added after 1 weeks....

i try and your code works correctly and not mine.... any explaination....if i change the "if count = N then" to be "if count = log(N) then" every 5 clk period it slow_clk make a transition... it is not correct....

how come different type can compare?... or if u include the unsigned package will make them compatible to each other??

thank you..
sp

 

[sp]

the "if count = N then" or "if count = log(N) then"

which one is correct?.. any explaination? anyone?

and one more question....

  function log ( n : integer) return integer is
    variable i : integer := 1;
    variable j : integer := 2;
  begin  -- log
    while (n - j > 0) loop
      j := j*2;
      i := i + 1;
    end loop;
    return i;
  end log;

how does anyone can figure out tht this is the method to do log function,,, i test wth my dirty hand calculation,, it is perfect,,,

is it get from trial and error or by some sort of algorithm????

thank you...

my regards,
sp

 

[nand_gates]

OK! here is the corrected code!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk_div is
  generic(N          :        positive := 10);
  port
    (fast_clk, reset : in     std_logic;
     slow_clk        : buffer std_logic
     );
end clk_div;

architecture behavioural of clk_div is
  function log ( n : integer) return integer is
    variable i : integer := 1;
    variable j : integer := 2;
  begin  -- log
    while (n - j > 0) loop
      j := j*2;
      i := i + 1;
    end loop;
    return i;
  end log;
begin
  process(reset, fast_clk)
    variable count : std_logic_vector(log(N/2) downto 0);
  begin
    if reset = '1' then
      count      := (others => '0');
      slow_clk   <= '0';
    elsif rising_edge(fast_clk) then
      count      := count + 1;
      if count = N/2 then
        slow_clk <= not slow_clk;
        count    := (others => '0') ;
      end if;
    end if;
  end process;
end behavioural;

the "if count = N then" is replaced by "if count = N/2 then"
which is correct one!
Other change I did is in the number of bits for count from log(N)
to log(N/2)+1.
*Note : this VHDL code works well only for even values for N

The log to the base 2 alogorithm is very simple one!
Log of N means how many times I need to multiply 2 by itself to get N
n - j in while loop checks for this equality!
Hope this helps you understand the code better!

 

[sp]

my question is .... can we compare using std_logic and positive type?...
like this one

if count = N/2 then

or when we include the "use ieee.std_logic_unsigned.all" then we can do tht?...
but when i compile it show no error....the previous code...

why u change to N/2? the previous code is correct.....anything wrong on using N and not N/2??

ya ya,, one more things,, for the prevous code using the N... when i do "if count = log(N) then" every 5 clk the slow clk change n not 10(which is the correct one).. i dont understand why also,,,

hehheh.. too many question,,,

thank you.....helped button pressed...

regards,
sp