zhaofeng1983
Member level 3
Now I am working on a 433MHz 8dBm PA with 2.5V supply at CMOS. The PA consist of two stages. The output stage works in Class AB mode while the preamplifier under Class A region.
A question: to obtain higher efficiency, I simulate the output stage with different input voltage and gate bias and obtain the optimum efficiency at about 0.7V bias with 1.1 Vamplitude input voltage. The threshold of the output stage is about 0.55V. The output stage and its pre-stage is AC coupled. Then I want to ask whether 1.1V(2.2Vpp) will deteriorate the output MOS transistor at the negtive side input?
Added after 6 minutes:
Still another question.
The optimum load impedance should be calculated with Zopt=Vdd/(2*Po), but I doubt whether this will work under my condition. Because about 500ohm may require 150nH choke which is not a good choice in my opinion. I get good efficiency performance at 33nH choke and 38-j175ohm optimum load. Is there any shortcoming in these data?
Added after 51 seconds:
THX
Added after 6 minutes:
When I changed the process corner, the output power also changes about 1.6dBm from SS coner to TT corner. In the work I have to control the output power with digital bits, thus I want to stable the power step in 3dB at different corners. But actually the power step varies with process variation greatly. How can I work on this problem?
Added after 42 minutes:
Finnally, how to determine the DC power consumption? The RF CMOS Power Amplifier by Hella and Ismal said that with initially estimation of 50% efficiency we can determine the gate bias voltage at some certain transistor size. I doubt his argumens for we should use average DC current to determine the DC power consumption but not DC bias current consumption. Is that right?
A question: to obtain higher efficiency, I simulate the output stage with different input voltage and gate bias and obtain the optimum efficiency at about 0.7V bias with 1.1 Vamplitude input voltage. The threshold of the output stage is about 0.55V. The output stage and its pre-stage is AC coupled. Then I want to ask whether 1.1V(2.2Vpp) will deteriorate the output MOS transistor at the negtive side input?
Added after 6 minutes:
Still another question.
The optimum load impedance should be calculated with Zopt=Vdd/(2*Po), but I doubt whether this will work under my condition. Because about 500ohm may require 150nH choke which is not a good choice in my opinion. I get good efficiency performance at 33nH choke and 38-j175ohm optimum load. Is there any shortcoming in these data?
Added after 51 seconds:
THX
Added after 6 minutes:
When I changed the process corner, the output power also changes about 1.6dBm from SS coner to TT corner. In the work I have to control the output power with digital bits, thus I want to stable the power step in 3dB at different corners. But actually the power step varies with process variation greatly. How can I work on this problem?
Added after 42 minutes:
Finnally, how to determine the DC power consumption? The RF CMOS Power Amplifier by Hella and Ismal said that with initially estimation of 50% efficiency we can determine the gate bias voltage at some certain transistor size. I doubt his argumens for we should use average DC current to determine the DC power consumption but not DC bias current consumption. Is that right?