Clarify a "An ADPLL Cicruit Using a DDPS for GENLOCK Applications" paper

[jadedfox]

hi,, is it possible to design pll(VCO part) using cadence virtuoso tool and then extract a verilog code of the VCO design for a fpga implementation...
i read in 1 paper the same way a vco design was done and then a VHDL code was extracted from some analog design tool for fpga implementation..

 

[AdvaRes]

dpll design

hi,, is it possible to design pll(VCO part) using cadence virtuoso tool and then extract a verilog code of the VCO design for a fpga implementation...
i read in 1 paper the same way a vco design was done and then a VHDL code was extracted from some analog design tool for fpga implementation..

Hi,

Could you please upload the paper or at least tell us its title/autors ?

Thanks.

 

[jadedfox]

vhdl dpll

AN ADPLL CIRCUIT USING A DDPS FOR GENLOCK APPLICATIONS
authors- Dorin Emil Calbaza, Ioan Cordos, Nigel Seth-Smith and Yvon Savaria

 

[AdvaRes]

verilog dpll

hi,, is it possible to design pll(VCO part) using cadence virtuoso tool and then extract a verilog code of the VCO design for a fpga implementation...
i read in 1 paper the same way a vco design was done and then a VHDL code was extracted from some analog design tool for fpga implementation..

I read your paper and I found only these sentences:

"Fig. 7 presents a micrograph of the active area of the Genlock
Chip. The NCXO was custom designed as an analog block, and
a VHDL model that emulates its functionality was created. The
other parts of the ADPLL were coded in VHDL and simulated
in combination with the NCXO’s VHDL model. The circuit was
synthesized and was fabricated in 0.18μm standard CMOS
technology"

In fact only the NCXO is really analog. The autors wrote manually a VHDL discription of this component in order to emulate its function . They didnt extract VHDL like you understood.