Clarifications in Characterizing NMOS and PMOS

[esdeath_123]

Hi. I've been wondering if it is alright to characterize PMOS and NMOS using same lengths and widths?

I was able to design a circuit and achieve the desired specs but the test circuits I used in characterizing, they have initial NMOS and PMOS lengths and widths of 90nm. In papers I read, however, the test width is always larger than the test length. Is this always the case? Or is what I did acceptable?

I also read somewhere that PMOS width is usually 2-3 times larger than NMOS but in the values I calculated (using gm/Id), my NMOS is larger than the PMOS. Should the PMOS width be always larger than the NMOS?

If someone can clarify these, it would be greatly appreciated.

 

[dr_kca]

PMOS mobility is lower than the NMOS therefore more width is required to reach similar amount of saturation current as an NMOS. This is valid for the case (and this is the most common case) where the designer wants balanced pull-up and pull-down currents.

 

[rmanalo]

I suggest visiting R. Jacob Baker's website on his https://cmosedu.com/jbaker/students/students.htm. Most of them start with characterization. What I noticed is that the first thing they do is match the transconductance behavior of NMOS and PMOS transistors by appropriately choosing the PMOS width.