[SOLVED] Clarification on if then else vhdl statements

[marika_ece]

hello everyone!

I am confused with the if then else sequential statements in VHDL.
Ex.1 In the construction below
if (condition1) then
statements1
else
statements2
end if;

are the statements under else(statements2) are executed regardless whether condition1 is TRUE or FALSE? In C programming, else statements are only executed when if condition is false.

Ex.1 In the construction below
if (condition1) then
statements1
elsif (condition2) then
statements2
elsif (condition3) then
statements2
end if;

are all elsif statements executed once their corresponding condition is true? Or is it like in C that only the first if or elsif statement which has a true condition is executed regardless whether the succeeding elsif conditions are true?

Hope to hear from you guys.

Thanks,

Marika

 

[FvM]

In C programming, else statements are only executed when if condition is false.

Yes, it's the only reasonable meaning of else. It's a simple matter of formal logic in my opinion. It's the same with elsif. You can be sure, that VHDL isn't less logical than C language.

 

[gck]

It is exactly like C programming language.

 

[marika_ece]

Thank you for your replies.

 

[Sameh Yassin]

AA,
Dear Marika:
It sounds that you are new to VHDL, the most important thing to note is that you are describing hardware, so there are some basic differences bewteen HDL and software programming.
You should know that when you wirte "if staement" in VHDL, that means that you are using a multiplexer from the FPGA resources.
However,"if statement" has the same function in both VHDL and software, but there is a basic difference that we call "Incomplete if", I'll just write an example to show the difference..
If (input = '1') then
output = '0'
end if;
this peace of code is more than okay when you write in C, but in VHDL you are using a 2x1 multiplexer that only has one input, that means how should the multipexer behave when intput ='0', so the synthesizer will add a latch to the other intput so that when input = '1' the output will latch the previous value..


If you want to master topics like this you should study the following topic "hdl synthesis" which describes the opertaion of the synthesizer and how our design entry is mapped into hardware.

best wishes for you,
Sameh Yassin
Cairo University

 

[oursriharsha]

[quoteIf you want to master topics like this you should study the following topic "hdl synthesis" which describes the opertaion of the synthesizer and how our design entry is mapped into hardware. [/quote]

Can u please suggest me some good resources , where i can get regarding the HDL synthesis , for the language that we use .

Thank you in advance.