Circumstances for using an inverter pair

[elecs_gene]

INVERTER PAIR

hi guys,
could u explain me at what circumstance is a synthesis compiler forced to put a inverter pair??is it because the usage of inverter pair makes the rise and fall time equal???

regards

 

[mystique_unbound]

Re: INVERTER PAIR

Rise times and falls times of Cmos inverter is didfferent because of diffenet mobilities of electrons and holes . In some case we need to have same rise and fall times . so use of inverter pair will make even delays tplh+tphl .

 

[Resistance]

Re: INVERTER PAIR

hi,

Inverter pairs are normally put in place to meet stingent timing constraints.
See u have to compensate by introducing comb delays so that the timing across two flops is met.

I dont think rise and fall got to do anything with this..

Regards.

 

[elecs_gene]

Re: INVERTER PAIR

hey resistance
what do u mean by saying stringent timing constraints???see,your ultimate aim is to minimize time..then,by adding inverters,u are going to increase the time...as far as i know,under no circumstance,would u specify a timing constraint that tells the synthesis compiler to increase existing timing..i agree ,u may have 2 inverters separated by a bufffer so as to probably boost the driving capability!!then,under what more circumstance does it generate the inverter pair???

regards

 

[leeenghan]

Re: INVERTER PAIR

Hi,

What I can think of is the fan-out is high. So the tool can put buffer, or use 2 inverters. Check if the first invertor only fanout to the second inverter (may be the first inverter also drive other logic).

Also, if you ask the tool the meet hold time, than this type of logic is expected.

Regards,
Eng Han