Circuit to test out Clock Tree Synthesis Algorithm

[buzzsaw]

Hi, recently I just designed a Clock Tree Synthesis optimization method, I would like to know if there are websites where I can find open-source RTL codings of circuits in Verilog format to test out my design. Would be good if the circuit has multiple clock source

 

[ThisIsNotSam]

it's hard to find designs that are a full SoC. But individual blocks there are plenty. Try opencores.org.

 

[ahmad898]

To find the example of circuits in verilog, search for the ISCAS 85 for combinational and ISCAS89 for sequential bechmarks.

 

[ThisIsNotSam]

To find the example of circuits in verilog, search for the ISCAS 85 for combinational and ISCAS89 for sequential bechmarks.

these are old and generally considered irrelevant. not to mention that ISCAS'85 have no flip flops, so no CTS is needed....

 

[rca]

RISC V free implementation exist....